Differential amplifier circuitry including: first and second main transistors of a given conductivity type; and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

A power detector with wide dynamic range. The power detector includes a linear detector, followed by a voltage-to-current-to-voltage converter, which is then followed by an amplification stage. The current-to-voltage conversion in the converter is performed logarithmically. The power detector generates a desired linear-in-dB response at the output. In this power detector, the distribution of gain along the signal path is optimized in order to preserve linearity, and to minimize the impact of offset voltage inherently present in electronic blocks, which would corrupt the output voltage. Further, the topologies in the sub-blocks are designed to provide wide dynamic range, and to mitigate error sources. Moreover, the temperature sensitivity is designed out by either minimizing temperature variation of an individual block such as the v-i-v detector, or using two sub-blocks in tandem to provide overall temperature compensation. In one aspect, active resistors are used in order to compensate for temperature variations.

A digitally controlled grounded capacitor multiplier includes: a single capacitor directly connected at one end to an input voltage and at another end to a negative input of an operational amplifier; the operational amplifier including a negative feedback loop; and a digitally controlled current amplifier (DCCA) connected to an output of the operational amplifier. The DCCA digitally controls the digitally controlled grounded capacitor multiplier. The digitally controlled grounded capacitor multiplier comprises only two active devices consisting of the operational amplifier and the DCCA.

The present disclosure relates to a gain stage for an amplifier and to the amplifier. The amplifier may be a broad-band amplifier, trans-impedance amplifier and/or driver amplifier. The gain stage includes a differential input transconductor, a loading network and a differential output terminal. Further, the gain stage includes at least one pair of inductances connected within the loading network or between the differential input transconductor and the differential output terminal.

An amplifier device and a duplexer circuit are provided. The amplifier device includes a first differential amplifier circuit and a controller. The first differential amplifier circuit includes first and second radio frequency (RF) input terminals, first and second transistors, first and second adjustable capacitor circuits, and first and second RF output terminals. The controller adjusts capacitance values of the first adjustable capacitor circuit of the first differential amplifier circuit and the second adjustable capacitor circuit of the first differential amplifier circuit according to at least one of a characteristic related to a first RF input signal of the first differential amplifier circuit, a characteristic related to the second RF input signal of the first differential amplifier circuit, a matching deviation between the first transistor and the second transistor of the first differential amplifier circuit, and a characteristic of the amplifier device.

A digitally controlled grounded capacitance multiplier circuit system and method is disclosed. The capacitance multiplier (CM) circuit comprises an op-amp, a digitally controlled current amplifier and two resistors in addition to a reference capacitor. The CM circuit is designed using complementary metal-oxide-semiconductor (CMOS) technology. The value of the equivalent capacitance can be adjusted through digitally programming the gain of the current amplifier. The CM circuit provides a significant multiplication factor while using two active devices.

An example VGA includes a transistor arrangement having a plurality of transistors configured to realize one or more gain step circuits of the VGA, and a cross-couple switching arrangement having a plurality of switches configured to selectively change the coupling of the terminals of at least some of the transistors depending on whether a given gain step circuit is supposed to be in an ON state or in an OFF state. Using the cross-couple switching arrangement advantageously allows keeping all of the transistors ON at all times during operation and changing the coupling of some transistor terminals to either realize an in-phase addition of currents flowing through various transistors to apply the maximum gain or realize a subtraction of currents to apply the minimum gain. Such a VGA may be inherently wideband, enabling a highly linear, wideband operation without having to resort to significant trade-offs with other performance parameters.

A variable-gain amplifier and a phased array system are provided. A variable-gain amplifier includes a cascode circuit comprising a first amplification transistor and a second amplification transistor array that are cascaded, the second amplification transistor array comprising a plurality of second amplification transistors connected in parallel and configured to output an adjustable current to an output matching network, the first amplification transistor is a common-source transistor, the plurality of second amplification transistors are common-gate transistors, or the cascode circuit is a common-emitter common-base circuit, the first amplification transistor is a common-emitter amplification circuit, and the second amplification transistor array is a common-base amplification circuit. The variable-gain amplifier further including a variable capacitor circuit coupled to the second amplification transistor array and coupled to the output matching network at first nodes.

An amplifier comprises a common emitter stage coupled to a first and a second input, a common base stage coupled to the common emitter stage and to a first and a second output, and a cancellation path coupled to the common emitter stage and the common base stage and to the first and second outputs. The cancellation path generates a first cancellation signal that is 180 degrees out of phase with a first leakage signal at the first output and a second cancellation signal that is 180 degrees out of phase with a second leakage signal at the second output. The cancellation path comprises a first cancellation transistor coupled to the common emitter stage and the common base stage and to the first output and a second cancellation transistor coupled to the common emitter stage and the common base stage and to the second output.

A power amplifier circuitry (100) comprises: a transistor stack (110) comprising at least two stacked transistor units (112A, 112B, 112C) for amplifying input signals; wherein each stacked transistor unit (112A, 112B, 112C) comprises a plurality of controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N), each comprising a segment transistor (122, 132, 142), wherein source terminals (123, 133, 143) within each transistor unit are connected, drain terminals (125, 135, 145) within each transistor unit are connected and gate terminals (124, 134, 144) within each transistor unit are connected, wherein each segment transistor (122, 132, 142) further comprises a back gate terminal (126, 136, 146) for setting a body bias, wherein at least two of the segment transistors (122, 132, 142) within each transistor unit have independently connected back gate terminals (126, 136, 146); and a control unit (190) configured to control the body bias for selecting an amplifier class of each of the controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N) of each of the stacked transistor units (112A, 112B, 112C).