A gain stage includes an offset cancellation loop coupled to a first amplifier. The first amplifier has a first transfer function and a first gain, and the offset cancellation loop includes a second amplifier having a second transfer function and a second gain. The second transfer function is based on an inverse of the first transfer function and the second gain based on an inverse of the first gain. When the offset cancellation loop feeds back an output signal of the first amplifier to an input of the first amplifier, a high-pass pole (or high-pass corner frequency) of the first amplifier is maintained at a constant level in spite of variations in the gain of the first amplifier. In one case, the second amplifier in the offset cancellation loop may be a simpler and lower power version of the first amplifier.

A gain stage includes an offset cancellation loop coupled to a first amplifier. The first amplifier has a first transfer function and a first gain, and the offset cancellation loop includes a second amplifier having a second transfer function and a second gain. The second transfer function is based on an inverse of the first transfer function and the second gain based on an inverse of the first gain. When the offset cancellation loop feeds back an output signal of the first amplifier to an input of the first amplifier, a high-pass pole (or high-pass corner frequency) of the first amplifier is maintained at a constant level in spite of variations in the gain of the first amplifier. In one case, the second amplifier in the offset cancellation loop may be a simpler and lower power version of the first amplifier.

Circuits comprising: a plurality of LNTA branches, each comprising: a cascode common-source (CCS) LNTA, a plurality of passive mixers (PMs), and a plurality of baseband two-stage Miller compensated TIAs (BB2S-TIAs); a plurality of mixer-first branches, each comprising: a plurality of RF switches, a plurality of baseband folded-cascode TIAs (BBFC-TIAs), and a plurality of Cherry-Hooper amplifiers, wherein an input to each of the BBFC-TIAs is provided by an output of at least one of the RF switches, and an input to each of the amplifiers is provided by an output of a corresponding one of the BBFC-TIAs; a first plurality of clock modulators that provide first non-overlapping modulated clocks that are provided to an input of the PMs; and a second plurality of clock modulators that provide a plurality of tri-level modulated mixer clocks that control the switching of the RF switches.

An amplifier includes a first input circuit, a second input circuit, a first compensation circuit, a second compensation circuit. The first input circuit changes a voltage level of the negative output node based on a first input signal. The second input circuit changes a voltage level of the positive output node based on a second input signal. The first compensation circuit changes the voltage level of the positive output node based on the first input signal. The second compensation circuit changes the voltage level of the negative output node based on the second output signal.

Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from a sampling circuit of one or more receiver arrangements that are not in autozero mode. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).

Circuits comprising: a plurality of LNTA branches, each comprising: a cascode common-source (CCS) LNTA, a plurality of passive mixers (PMs), and a plurality of baseband two-stage Miller compensated TIAs (BB2S-TIAs); a plurality of mixer-first branches, each comprising: a plurality of RF switches, a plurality of baseband folded-cascode TIAs (BBFC-TIAs), and a plurality of Cherry-Hooper amplifiers, wherein an input to each of the BBFC-TIAs is provided by an output of at least one of the RF switches, and an input to each of the amplifiers is provided by an output of a corresponding one of the BBFC-TIAs; a first plurality of clock modulators that provide first non-overlapping modulated clocks that are provided to an input of the PMs; and a second plurality of clock modulators that provide a plurality of tri-level modulated mixer clocks that control the switching of the RF switches.

A current feed-back instrumentation amplifier (CFIA) comprises a differential pair with degeneration for amplifying small differential voltages in the presence of large common-mode voltages. The CFIA includes input and feedback transconductors and a trimming circuit that trims the back-bias voltages of the transistors in each transconductor. The trimming circuit includes a plurality of selectable resistors disposed in the signal path of the tail current in each transconductor. Each of the plurality of selectable resistors has a switch coupled to it. When a switch is closed, only the resistors up to the respective switch are in the signal path of the bulk-to-source voltage of the differentially paired transistors. The resistor trimming circuit reduces the mismatch between transconductances of the respective differential pair transistors, in turn reducing mismatch of the overall transconductances of the transconductors, and thereby reducing the CFIA's gain error.

A high-efficiency high-integrated receiver is provided. The radar receiver according to an embodiment of the present disclosure includes a receiver configured to receive a radar signal, a processor configured to attenuate a magnitude of a low frequency band of the received signal of the receiver, a filter configured to perform a low pass filtering on an output signal of the processor, and an ADC configured to A/D convert the output signal of the filter. Accordingly, it is possible to demodulate all the signals being reflected from targets in various distances when even using a low resolution ADC, thereby reducing the manufacturing cost and power consumption.

A semiconductor integrated circuit has a reception circuit configured to receive a strobe signal of which a logic is intermittently switched in synchronization with a data signal, an output circuit configured to extract a low frequency component including at least a DC component of the strobe signal received by the reception circuit and to output a first signal, and a comparison circuit configured to compare a signal level of the first signal with a threshold level. The reception circuit is configured to change a boost amount of a high frequency component different from the low frequency component of the strobe signal based on a comparison result obtained by the comparison circuit.

Certain aspects of the present disclosure generally relate to a differential amplifier implemented using a complementary metal-oxide-semiconductor (CMOS) structure. The differential amplifier generally includes a first pair of transistors and a second pair of transistors coupled to the first pair of transistors. The gates of the first pair of transistors and gates of the second pair of transistors may be coupled to respective differential input nodes of the differential amplifier, and drains of the first pair of transistors and drains of the second pair of transistors may be coupled to respective differential output nodes of the differential amplifier. In certain aspects, the differential amplifier may include a biasing transistor having a drain coupled to a source of a transistor of the first pair of transistors and having a gate coupled to a common-mode feedback (CMFB) path of the differential amplifier.