To provide a semiconductor device that makes it possible to reduce a cell circuit area and an increase in resolution. There is provided a semiconductor device including: a first region in which readout cells are arranged in an array form, the readout cells having one of input transistors included in a differential amplifier: and a second region in which reference cells are arranged in an array form, the reference cells having another input transistor included in the differential amplifier, the first region and the second region being separated from each other.

A device for buffering a reference signal comprises a regulator circuit configured to generate at least two replicas of the reference signal as regulated output signals. The device further comprises a receiving circuit configured to receive the regulated output signals in a switchable manner. In this context, the regulated output signals are configured to have different performance characteristics.

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.

The disclosure provides a circuit. The circuit includes a gain stage block. The gain stage block is coupled to an input voltage through a first switch. A first capacitor is coupled between the first switch and a ground terminal. A second capacitor is coupled between the first switch and a second switch. A third switch is coupled between the second capacitor and a fixed terminal of the gain stage block.

An amplifier circuit includes a first input branch circuit including a first sampling capacitor, a second input branch circuit including a second sampling capacitor, an averaging capacitor, and a subtraction capacitor, a feedback capacitor, and an operational amplifier. The first sampling capacitor samples an input voltage in a first time period and outputs a first voltage. The second sampling capacitor samples the input voltage in the first time period and outputs a second voltage. The averaging capacitor takes an average of the second voltage in the second time period and outputs a third voltage. The subtraction capacitor receives the third voltage in the first time period. The subtraction capacitor subtracts the first voltage from the third voltage and outputs a fourth voltage in the second time period. The operational amplifier is connected to the feedback capacitor and amplifies the fourth voltage. The first and second time periods are repeated alternately.

The present invention discloses a programmable gain amplifier having mode-switching mechanism. An operational amplifier includes a first input terminal, a second input terminal and an output terminal. The second input terminal is coupled to a ground terminal. The output terminal generates an output signal. A variable resistor and a first switch are coupled in series between a first terminal and a second terminal that coupled to the first input terminal. A first variable capacitor and a second switch are coupled in series between the first terminal and the second terminal. A second variable capacitor and a third switch are coupled in series between the first terminal and the ground terminal. A low-pass resistor and a low-pass capacitor are coupled in parallel between the first input terminal and the output terminal. An input resistor is coupled between a signal input terminal and the first terminal to receive an input signal from the signal input terminal. The first, the second and the third switches receive a set of mode-switching signals to switch to form a path or an open-circuit.

A program gain amplifier includes an operational amplifier and a capacitor array. The capacitor array includes a first, second, and third capacitors selectively coupled to the operational amplifier or ground according to a first, second, and third switches, respectively. The first, second, and third capacitors have a first, second, and third capacitance, respectively. The third capacitance equals a sum of the first and second capacitance. In a first configuration, the first and second switches are operated at a first conductive state, and the third switch is operated at a second conductive state. When converting to a second configuration from the first configuration, the third switch is operated at the first conductive state, and the first and second switches are operated at the second conductive state. The gain being provided to an input signal in the first and second configurations are the same.

An amplifying circuit includes a reference voltage generating circuit, a common-mode voltage conversion circuit, a common-mode negative feedback circuit, and an amplifying sub-circuit. The reference voltage generating circuit generates a first reference voltage, a second reference voltage, and a reference common-mode voltage according to a post-stage common-mode voltage. The common-mode voltage conversion circuit converts the pre-stage output differential signal into a differential input signal according to the reference common-mode voltage. The common-mode negative feedback circuit generates a control voltage to quickly establish a common-mode negative feedback of the amplifying sub-circuit, wherein the first reference voltage and the second reference voltage are used to cancel a baseline signal of the pre-stage output differential signal. The amplifying circuit can eliminate the baseline signal, convert the common-mode voltage and quickly establish the common-mode negative feedback.

Herein disclosed are multiple embodiments of a signal-processing circuit that may be utilized in various circuits, including conversion circuitry. The signal-processing circuit may receive an input and produce charges on multiple different capacitors during different phases of operation based on the input. The charges stored on two or more of the multiple different capacitors may be utilized for producing an output of the signal-processing circuit, such as by combing the charges stored on two or more of the multiple different capacitors. Utilizing the charges on the multiple different capacitors may provide for a high level of accuracy and robustness to variations of environmental factors, and/or a low noise level and power consumption when producing the output.

An integrator includes a first switch, a first capacitor, a second switch, a second capacitor, an amplifier, a third switch, a forth switch, a third capacitor, and a control circuit. The control circuit repeats a first phase and a second phase. In the first phase, the control circuit renders the first switch and the third switch to turn on and the second switch and the fourth switch to turn off. In the second phase, the control circuit renders the second switch and the fourth switch to turn on and the first switch and the third switch to turn off.