The present invention provides a circuit including a reference voltage generator and a plurality of receivers, wherein the reference voltage generator is configured to generate a reference voltage, and each of the receivers is configured to receive the reference voltage and a corresponding input signal to generate a corresponding output signal. In addition, for at least a specific receiver of the plurality of receivers, the specific receiver comprises at least one amplifying stage, the amplifying stage comprises a first input terminal configured to receive the corresponding input signal, a second input terminal configured to receive the reference voltage, a first output terminal configured to generate a first signal, and a second output terminal configured to generate a second signal; and the specific receiver further comprises a first feedback circuit coupled between the first output terminal and the second input terminal.

In examples, an apparatus for sensing current comprises a power transistor; a sense transistor coupled to the power transistor; and an offset addition circuit coupled to the power transistor and the sense transistor, the offset addition circuit comprising a first pair of transistors and a differential amplifier. The apparatus also comprises a cascode amplifier circuit coupled to the offset addition circuit, the cascode amplifier circuit comprising a second pair of transistors, and a gain trim circuit coupled to the cascode amplifier circuit, the gain trim circuit including another differential amplifier and a third transistor. The apparatus further includes an analog-to-digital converter (ADC) coupled to the gain trim circuit and storage coupled to the ADC.

An analog-to-digital converter (10) comprises a first and a second sampling capacitor (24, 25), a first integrator (26), a first and a second input switch (31, 32) coupling a first input terminal (11) and a common mode terminal (39) to a first electrode of the first sampling capacitor (24), a third and a fourth input switch (33, 34) coupling a second input terminal (12) and the common mode terminal (39) to a first electrode of the second sampling capacitor (25), a fifth and a sixth input switch (35, 36) coupling a second electrode of the first sampling capacitor (24) to an amplifier common mode terminal (40) and the first integrator input (27), and a seventh and an eighth input switch (37, 38) coupling a second electrode of the second sampling capacitor (25) to the amplifier common mode terminal (40) and the second integrator input (28).

A gain amplifier of a sensing circuit for sensing degradation of an OLED display panel, the gain amplifier comprising: an operation amplifier; and a plurality of gain amplifier cells sequentially coupled to the operation amplifier. Each of the gain amplifier cells comprises a plurality of capacitors each placed between two internal nodes of the gain amplifier cell, excluding a ground node, such that a voltage gain of the gain amplifier and a DC offset of the gain amplifier are determined according to capacitances of the capacitors without considering parasitic capacitance.

An operational amplifier circuit includes a potential control circuit connected between a current sense semiconductor element connected in parallel with a main semiconductor element and a current detection resistor. The potential control circuit controls an output potential of the current sense semiconductor element to be equal to that of the main semiconductor element. The potential control circuit includes a current control element controlling an output current of the current sense semiconductor element and an operational amplifier outputting a signal corresponding to an output potential difference between the current sense semiconductor element and the main semiconductor element to the current control element. An input offset voltage polarity determination unit determines a polarity of an input offset voltage of the operational amplifier according to the output potential difference. The polarity of the input offset voltage is controlled to be constant based on polarity determination of the input offset voltage.

An electronic device test system includes a contactor having probe pairs with first and second conductive probes to couple to a respective conductive feature of a packaged electronic device or wafer die region. The system also includes a test circuit having a voltage source to provide a common mode voltage signal; a first buffer with a first input coupled to an output of the voltage source, an output coupled to a first conductive probe of a first probe pair, and a second input coupled to a second conductive probe of the first probe pair; and a second buffer with a first input coupled to the output of the voltage source, an output coupled to a first conductive probe of a second probe pair, and a second input coupled to a second conductive probe of the second probe pair.

A leakage compensation circuit includes a buffer amplifier, a link coupling element, and a leakage compensation element. The buffer amplifier has an input coupled to a sense node, and an output. The link coupling element has an input coupled to the output of the buffer amplifier, and an output, wherein the link coupling element is unidirectional in a direction from the input to the output thereof. The leakage compensation element has a first current terminal coupled to the sense node, a control terminal coupled to the output of the link coupling element, and a second current terminal coupled to a reference voltage terminal.

A high-to-low voltage interface circuit includes a differential circuit stage with a differential amplifier circuit having inverting and non-inverting inputs coupled to first and second input pads as well as a differential output having first and second output nodes. A pair of bias amplifier stages sensitive to the common mode voltage of the differential amplifier circuit are arranged in first and second current mirror paths from the first and second input pads to the inverting/non-inverting inputs of the differential amplifier circuit, respectively. The bias amplifier stages are configured to maintain the first input pad and the second input pad of the differential circuit stage at the common mode voltage.

Briefly, embodiments of claimed subject matter relate to determination of a high-impedance state or a low-impedance state of a resistive memory element over a wide range of temperature, such as temperatures approaching 40.0 C. to temperatures approaching +125.0 C. Such determination may be brought about by implementing a circuit which, according to various embodiments described herein, emulates a reference impedance having a negative temperature coefficient.

A read-out circuitry for acquiring a multi-channel biopotential signal, comprises: a plurality of read-out signal channels, each receiving an input signal from a unique signal electrode; a reference channel receiving a reference signal from a reference electrode; wherein each read-out signal channel and the reference channel comprises a channel amplifier connected to receive the input signal in a first input node and with an output node connected to a second input node via a channel feedback loop; wherein each signal channel amplifier comprises a capacitor between the second input nodes of the signal channel amplifier and the reference channel amplifier, and wherein each signal channel feedback loop and the reference channel feedback loop comprise a filter.