An amplifier includes input transconductors that receive an input signal, the input signal having a voltage swing. A supply side current mirror generates a gate voltage as a function of input signal voltage and current sources that provide a bias current of the input transconductors as a function of the gate voltage to maintain a constant bias current across the voltage swing of the input signal. Resistors average source voltages of the transconductance-cancelling transconductors to provide an average source voltage and apply the average source voltage to wells of input devices of the transconductance-cancelling transconductors to reduce back bias effect. The input devices are laid out in a same well and have a common centroid to cancel out process mismatches. A first I-DAC trims an offset of first transconductors, and a second I-DAC trims an offset of second transconductors to attain low offsets across a rail-to-rail input common mode range.

Sampling circuits and methods for sampling are provided. In a first operating phase, sampling capacitors are coupled to inputs, and in a second operating phase, to a common-mode signal.

A detector circuit for galvanically isolated transmission of digital signals. The detector circuit includes two differential signal inputs, one input common-mode voltage connection, one alternating voltage coupling, and one differential stage. The detector circuit also includes one operating voltage connection, one operating ground connection, one signal output, one bias current connection, and one rectifier stage. The alternating current coupling includes two capacitors and two resistors. The differential stage includes a first n-channel transistor and a second n-channel transistor. The bias current connection is connected to the differential stage via a third n-channel transistor. The bias current connection is connected to the rectifier stage via a fourth n-channel transistor and a fifth n-channel transistor. The rectifier stage includes five p-channel transistors.

A circuit includes a first amplifier having first and second inputs and first and second output, first and second input capacitors, a first feedback capacitor selectively coupled between the first input and the first output, and a second feedback capacitor selectively coupled between the second input and the second output. During a second phase of operation, the first and second feedback capacitors are decoupled from the output and the first amplifier is configured to sample an input common mode voltage, an output common mode voltage, and an input offset voltage of the first amplifier on the first and second input capacitors. During a first phase of operation, the first feedback capacitor is coupled between the input and the output, the second feedback capacitor is coupled between the input and the output, and the first amplifier is configured to amplify a differential input signal provided across the first and second inputs.

An example apparatus includes: a first voltage source, a first amplifier having a noninverting input adapted to be coupled to a photodiode anode and coupled to the first voltage source, an inverting input adapted to be coupled to a photodiode cathode, and an output, a first resistor coupled to the first amplifier inverting input and to the first amplifier output, a first capacitor coupled to the inverting input of the first amplifier and the first amplifier output, and a second voltage source different from the first voltage source. There is a second amplifier having a noninverting input, an inverting input and an output. The noninverting input is coupled to the output of the first amplifier, the inverting input is coupled to the second voltage source, and there is a second resistor coupled to the inverting input and the output of the second amplifier.

Apparatus for performing offset cancellation is disclosed. The apparatus comprises a gating circuit (6) for receiving an analogue signal (3) from a source (2) and providing a gated analogue signal (9) to an analogue circuit (10), a gating controller (7; 14; FIG. 1) and a digital processor (14; FIG. 1) for receiving a digital signal (13) converted from an analogue output (11) from the analogue circuit (10). The gating circuit comprises at least one path (21.sub.1), each path respectively comprising, an input terminal (22.sub.1), an output terminal (23.sub.1), a node (24.sub.1) interposed between the input and output terminals, a first transistor (Q1) having a channel arranged between the input terminal and the node, and a second transistor (Q3) having channel arranged between the node and a fixed reference, such as ground (GND). The gating controller is configured, in a first time window (15.sub.A), to switch the first transistor so that the input terminal and the output terminal are decoupled and to switch the second transistor so that the node is coupled to the fixed reference. The gating controller is configured, in a second, different time window (15.sub.B), to switch the second transistor so that the node and the fixed reference are decoupled and to switch the first transistor so that the input terminal is coupled to the input terminal. The digital processor is configured, in the first time window, to take a first measurement of the digital signal, and, in the second, different time window, to take a second measurement of the digital signal. The digital processor configured to subtract the first measurement from the second measurement.

A semiconductor device includes an output driving circuit configured to output an output current to an output terminal; a detection resistor connected between the output terminal and the output driving circuit; an amplification unit configured to output an analog detection signal generated by amplifying a voltage between both ends of the detection resistor; a current generation circuit configured to output a reference current; a reference resistor connected between the current generation circuit and a ground and configured to output a reference voltage according to the reference current; an A/D converter configured to convert the analog detection signal into a digital detection signal using the reference voltage as a reference; and a control circuit configured to control the output current output from the output driving circuit according to the digital detection signal. The detection resistor has a same temperature characteristics as the reference resistor.

A leakage compensation circuit includes a buffer amplifier, a link coupling element, and a leakage compensation element. The buffer amplifier has an input coupled to a sense node, and an output. The link coupling element has an input coupled to the output of the buffer amplifier, and an output, wherein the link coupling element is unidirectional in a direction from the input to the output thereof. The leakage compensation element has a first current terminal coupled to the sense node, a control terminal coupled to the output of the link coupling element, and a second current terminal coupled to a reference voltage terminal.

A circuit includes a first amplifier having first and second inputs and first and second output, first and second input capacitors, a first feedback capacitor selectively coupled between the first input and the first output, and a second feedback capacitor selectively coupled between the second input and the second output. During a second phase of operation, the first and second feedback capacitors are decoupled from the output and the first amplifier is configured to sample an input common mode voltage, an output common mode voltage, and an input offset voltage of the first amplifier on the first and second input capacitors. During a first phase of operation, the first feedback capacitor is coupled between the input and the output, the second feedback capacitor is coupled between the input and the output, and the first amplifier is configured to amplify a differential input signal provided across the first and second inputs.

A current sensing circuit includes a current sense amplifier and a correction circuit. The current sense amplifier has an offset voltage. The correction circuit is configured to evaluate the offset voltage of the current sense amplifier. The correction circuit is further configured to issue a correction signal to the current sense amplifier based upon the evaluated offset voltage. The correction signal is to adjust the offset voltage.