A semiconductor circuit comprising an input block having a first chopper providing a chopped voltage signal, a first transconductance converting said chopped voltage signal into a chopped current signal, a second chopper providing a demodulated current signal, a current integrator having an integrating capacitor providing a continuous-time signal, a first feedback path comprising: a sample-and-hold block and a first feedback block, the first feedback path providing a proportional feedback signal upstream of the current integrator. The amplification factor is at least 2. Charge stored on the integrating capacitor at the beginning of a sample period is linearly removed during one single sampling period. Each chopper operates at a chopping frequency. The sample-and-hold-block operates at a sampling frequency equal to an integer times the chopping frequency.

An apparatus, including: a buffer configured to receive an input differential signal and generate an output signal based on the input differential signal, wherein the buffer includes a first buffer stage including: a first field effect transistor (FET); a second FET coupled in series with the first FET between a first voltage rail and a second voltage rail; a third FET; a fourth FET coupled in series with the third FET between the first voltage rail and the second voltage rail, wherein the first and third FETs include gates coupled together, and wherein the second and fourth FETs include gates configured to receive positive and negative components of the input differential signal; and a first capacitor coupled between a drain of the second FET and the gates of the first and third FETs.

A dual operation mode power amplifier is disclosed. In the power amplifier in accordance with an embodiment of the present invention, a bias circuit part can be converted to decrease power consumption. Different from the prior art, performance of the present invention is not reduced in a high power mode, and no additional passive components like inductors or transformers with a large area are necessary to be further added. Furthermore, a tunable impedance matching circuit provides impedances respectively matching impedances of a fully differential amplifier and a single-ended amplifier, thereby improving the performance of the power amplifier.

A travelling wave amplifier (TWA) with a widened frequency bandwidth is disclosed. The TWA include input transmission lines, amplifier units connected in parallel between the input terminal and the out terminal of the TWA. Each of the amplifier units configures an emitter follower in the front end thereof and an amplifying section. A feature of the TWA is that compensation units that compensates the high frequency performance of the TWA are implemented in the input transmission lines and/or integrated with the amplifier units.

An amplifier circuit with improved accuracy is provided that comprises a cascade of amplifier stages, a control line for controlling the amplifier stages, a feedback circuit having an input port for receiving a reference signal, and a feedback loop connecting the feedback circuit to the control line. Via the feedback circuit and the feedback loop, the large signal behavior of the amplifier stage is accurately fixed. As a result, the small signal gain of the amplifier stages has an improved accuracy as well.