A current sensing circuit includes load transistors having a current path coupled between a power terminal and corresponding load terminals, sense transistors having a current path coupled between the power terminal and corresponding sense terminals, each sense transistor being coupled to a respective load transistor, N-channel transistors having a current path coupled between a respective sense transistor and a respective sense terminal, an amplifier for selectively equalizing the voltages across one of the load transistors and one of the sense transistors, and bypass circuits coupled to a bulk terminal of the N-channel transistors.

A method and apparatus of global coarse baseline correction (GCBC) for capacitive scanning. An input device may include a number (N) of sensor electrodes, a GCBC circuit, and detection circuitry. Each sensor electrode is associated with a respective channel. The GCBC circuit produces sensing signals in each of the N channels and the detection circuitry may detect changes in the capacitances of one or more sensor electrodes based on the sensing signals. In some implementations, the GCBC circuit may include a current source which outputs a first current, a transimpedance amplifier (TIA) which converts the first current to a sensing voltage, and a number (N) of resistors that can be coupled between the output of the TIA and the N sensor electrodes, respectively. The coupling of each resistor between the TIA and a respective sensor electrode produces a sensing signal in the channel associated with the sensor electrode.

The present invention relates to a sensing circuit with signal compensation, which comprises a first sensing element, a second sensing element and a differential amplifying circuit, the differential amplifying circuit generates an output signal through a differential compensation according to a common mode voltage, a first sensing signal and a second sensing signal. Hereby, reducing the noise of the sensing circuit is achieved, and the interference of the display driving signal may be effectively improved.

An amplifier circuit is capable of switching between a unipolar output voltage domain and a bipolar output voltage domain. The amplifier circuit comprises an operational amplifier with a feedback circuit that is configurable using switches. By controlling the switches, the amplifier's feedback circuit can switched between two different arrangements having a positive and a negative signal gain, respectively. The amplifier circuit is designed such that the noise gain is the same in both operating modes, allowing a single noise compensation approach to be used for both operating modes. Since configurability of the circuit is achieved using static switches, the amplifier circuit maintains high accuracy and experiences no appreciable impact on power consumption as a result of implementing the switching.

An inverted group delay circuit is provided. The inverted group delay circuit can offset a group delay between a pair of signals. In a non-limiting example, the inverted group delay circuit can be configured to offset a group delay (e.g., negative group delay) between a time-variant voltage and a time-variant envelope of an analog signal. More specifically, the inverted group delay circuit can output an inverted time-variant voltage having an opposing phase and time-adjusted relative to the time-variant voltage to thereby offset the group delay between the time-variant voltage and the time-variant envelope. As such, the inverted group delay circuit can be provided in a power management integrated circuit (PMIC) to improve timing alignment between a time-variant voltage(s) and a time-variant analog signal(s) at a power amplifier(s), thus helping to reduce potential amplitude distortion when the analog signal(s) is amplified by the power amplifier(s).

According to an aspect, an auto-zero amplifier includes a main amplifier, a secondary amplifier connected to the main amplifier, a plurality of switching including a first switch and a second switch, and a leakage control circuit.

A transceiver includes a first common T-coil circuit coupled to a first input-output pin of the transceiver, a termination impedance coupled to the first common T-coil circuit and configured to match an impedance of a transmission line coupled to the first common T-coil circuit, an amplifier configured to receive an input signal from the first input-output pin through the first common T-coil circuit based on a receive enable signal, and a first transmission buffer configured to transmit an output signal to the first input-output pin through the first common T-coil circuit based on a transmit enable signal.

A receiver includes a first T-coil circuit at an input of the receiver and configured to receive an input signal, a termination impedance coupled to the first T-coil circuit and configured to match an impedance of a transmission line coupled to the first T-coil circuit, and an amplifier including a first input and a second input and configured to amplify a differential signal at the first and second inputs, a calibration switch coupled to the amplifier and configured to selectively electrically connect or disconnect the first and second inputs of the amplifier, and a first receive switch configured to selectively electrically connect or disconnect a center node of the first T-coil circuit and the amplifier.

Chopper amplifiers with tracking of multiple input offsets are disclosed herein. In certain embodiments, a chopper amplifier includes chopper amplifier circuitry including an input chopping circuit, an amplification circuit, and an output chopping circuit electrically connected along a signal path. The amplification circuit includes two or more pairs of input transistors, from which a control circuit chooses a selected pair of input transistors to amplify an input signal. The chopper amplifier further incudes an offset correction circuit that senses the signal path to generate an input offset compensation signal for the amplification circuit. Furthermore, the offset correction circuit separately tracks an input offset of each of the two or more pairs of input transistors.

A circuit arrangement comprises a first input node, a first output node, a sampling capacitor means and a first switching means being switchable between a first switching state and a second switching state. The first switching means is coupled to the sampling capacitor means, the first input node and the first output node in such a way that the sampling capacitor means is conductively connected to the first input node and disconnected from the first output node in the first switching state and the sampling capacitor means is disconnected from the first input node and conductively connected to the first output node in the second switching state. A first charge-storing element is coupled via a second switching means to the first input node in such a way that the charge-storing element is charged in the first switching state and discharged in the second switching state, thereby at least partly compensating current flow for charging the sampling capacitor means in the first switching state.