The present disclosure discloses a harmonic rejection mixing circuit device and a receiver. In the harmonic rejection mixing circuit device, outputs of first and fourth mixers are combined with the input terminal of the fourth mixer being connected to a capacitor, the first mixer samples a first group of local oscillator (LO) signals, and the fourth mixer phase-invertedly samples the first group of LO signals, thus the noise introduced by a fundamental LO signal input to the first mixer may be eliminated using the double balance feature of the fourth mixer core, thereby ensuring a high signal-to-noise ratio of the receiver. Similarly, the noises introduced by fundamental LO signals input to second and third mixers may be eliminated respectively using the double balance features of the fifth and sixth mixer cores, thereby lowering the noise figure to ensure a high signal-to-noise ratio of the receiver.

A method for matching a pair of composite circuit elements (CEs) included in a circuit includes fabricating N CEs (e.g., resistors, transistors, current sources, capacitors) designed to match and switches configurable, according to M different combinations, to connect N/2 of the N CEs to form a first composite CE and to connect a remaining N/2 of the N CEs to form a second composite CE. Sequentially in time, for each combination of the M combinations, the switches are configured to form the first and second composite CEs according to the combination and a characteristic of the circuit is measured that includes the formed first and second composite CEs. The characteristic indicates how well the formed composite CEs match. A final combination of the M combinations is chosen whose measured characteristic indicates a best match and the final combination is used to configure the switches to form the composite CEs.

An amplifier system with high gain, compact size, and extended bandwidth is disclosed. The amplifier system includes one or more inputs configured to receive one or more input signals and a pre-driver configured to receive the one or more input signals. The pre-driver may comprise source connected FETs which create a virtual ground and may include inductors which cancel or counter parasitic capacitance of the FETs. The pre-driver amplifies the one or more input signals to create one or more pre-amplified signals, which are provided to a voltage divider network configured to reduce a DC bias voltage of the one or more pre-amplified signals, while maintaining a wide bandwidth range. An amplifier receives and amplifies the output of the voltage divider network to create amplified signals. The amplifier may comprise mirrored FET pairs in a common source configuration and a common gate arrangement.

The driver circuit includes DC cut capacitors, an input buffer, input termination resistors connected in series between differential input signal terminals and an ESD protection circuit connected to a connection point of the input terminal resistors. The ESD protection circuit includes diodes.

A circuit includes a first transconductance stage having an output. The circuit further includes an output transconductance stage, and a first source-degenerated transistor having a first control input and first and second current terminals. The first control input is coupled to the output of the first transconductance stage. The circuit also includes a second transistor having a second control input and third and fourth current terminals. The third current terminal is coupled to the second current terminal and to the output transconductance stage.

An amplifier has a first amplifying circuit configured to receive a voltage input and to output an amplified current, a second amplifying circuit configured to receive the amplified current and to output an amplified voltage, the second amplifying circuit comprising a pair of feedback resistive elements, each feedback resistive element being coupled to a gate and drain of a corresponding transistor in a pair of output transistors in the second amplifying circuit, and a feedback circuit configured to provide a negative feedback loop between an input and an output of the pair of output transistors, the feedback circuit including a first transconductance amplification circuit and a first equalizing circuit.

A circuital system that includes a differential low-pass filter having a differential output and operable in a first voltage domain. Some embodiments include a differential integrator including a differential input and a differential output, and operable in a second voltage domain different from the first voltage domain. Some embodiments include a pair of AC coupling capacitors coupling the differential output of the differential low-pass filter to the differential input of the differential integrator.

Multifunctional RF limiting amplifiers having various configurations and functions are disclosed. In a first configuration, the RF limiting amplifier includes an active load output circuit that allows one to adjust the output impedance based upon the anticipated connected load impedance. In a second configuration, the RF limiting amplifier includes a pair of emitter-followers to buffer the output of a first stage, allowing the RF limiting amplifier to drive one or more second stages. A third configuration includes a pair of RF limiting amplifiers with their outputs mixed to implement a down conversion function. The third configuration may be used to drive dual SAW resonators for detecting the presence of biological or chemical agents. The RF limiting amplifier may be implemented in either bipolar junction transistors or CMOS transistors.

A circuital system that includes a differential low-pass filter having a differential output and operable in a first voltage domain. Some embodiments include a differential integrator including a differential input and a differential output, and operable in a second voltage domain different from the first voltage domain. Some embodiments include a pair of AC coupling capacitors coupling the differential output of the differential low-pass filter to the differential input of the differential integrator.

A power amplifier circuit includes a first transistor having an emitter electrically connected to a common potential, a base to which a first high-frequency signal is input, and a collector from which a third high-frequency signal is output; a second transistor having an emitter electrically connected to the common potential, a base to which a second high-frequency signal is input, and a collector from which a fourth high-frequency signal is output; a first capacitance circuit electrically connected between the collector of the second transistor and the base of the first transistor; and a second capacitance circuit electrically connected between the collector of the first transistor and the base of the second transistor.