A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. A output passive network can further generate a flat-phase response between dual resonances of operation.

An RF amplifier for implementation in SiGe HBT technology is described. The RF amplifier has a cascode stage comprising a common base (CB) transistor and a common emitter (CE) transistor arranged in series between a first voltage rail and a second voltage rail. An RF input is coupled to the base of the CE transistor and an RF output is coupled to the collector of the CB transistor. The RF amplifier includes a CB power-down circuit arranged between the base of the CB transistor and the second voltage rail and a CE power-down circuit arranged between the base of the CE transistor and the second voltage rail. In a power-down mode the CE power-down circuit couples the base of the common-emitter-transistor to the second voltage rail. The CB power-down mode circuit couples the base of the CB transistor to the second voltage rail via a high-ohmic path.

A successive approximation analog-to-digital with an input for receiving an input analog voltage, and an amplifier with a first set of electrical attributes in a sample phase and a second set of electrical attributes, differing from the first set of electrical attributes, in a conversion phase.

According to one embodiment, a high frequency amplifier circuit includes a first transistor including a gate to which an input signal is input; a second transistor including a gate grounded, and a source coupled to a drain of the first transistor; a first switch coupled between a first output terminal and a first node located between the drain of the second transistor and an inductor; a third transistor including a gate to which the input signal is input; a fourth transistor including a gate that is grounded, and a source coupled to a drain of the third transistor; a second switch coupled between a second output terminal and a second node located between the drain of the fourth transistor and an inductor; and a third switch coupled between the first node and the second node.

A method and network equipment for controlling power amplification are disclosed. The method for controlling power amplification includes outputting a voltage signal according to the state of network equipment. When the network equipment is in an idle state, at least one power amplifier transistor is switched off according to a voltage signal.

A receiver front end amplifier capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors, and gate to ground capacitors for each leg can be used to further improve the matching performance of the invention.

Methods for operating amplifiers and related devices. In some embodiments, a method for amplifying a signal can include partially amplifying a signal with a common amplification stage. The method can further include providing a bias signal to a selected one of a plurality of dedicated amplification stages each coupled to the common amplification stage and including an output node, such that the selected dedicated amplification stage further amplifies the partially amplified signal and provides the further amplified signal at the respective output node.

Chopper amplifiers with tracking of multiple input offsets are disclosed herein. In certain embodiments, a chopper amplifier includes chopper amplifier circuitry including an input chopping circuit, an amplification circuit, and an output chopping circuit electrically connected along a signal path. The amplification circuit includes two or more pairs of input transistors, from which a control circuit chooses a selected pair of input transistors to amplify an input signal. The chopper amplifier further incudes an offset correction circuit that senses the signal path to generate an input offset compensation signal for the amplification circuit. Furthermore, the offset correction circuit separately tracks an input offset of each of the two or more pairs of input transistors.

A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. A output passive network can further generate a flat-phase response between dual resonances of operation.

An RF amplifier for implementation in SiGe HBT technology is described. The RF amplifier has a cascode stage comprising a common base (CB) transistor and a common emitter (CE) transistor arranged in series between a first voltage rail and a second voltage rail. An RF input is coupled to the base of the CE transistor and an RF output is coupled to the collector of the CB transistor. The RF amplifier includes a CB power-down circuit arranged between the base of the CB transistor and the second voltage rail and a CE power-down circuit arranged between the base of the CE transistor and the second voltage rail. In a power-down mode the CE power-down circuit couples the base of the common-emitter-transistor to the second voltage rail. The CB power-down mode circuit couples the base of the CB transistor to the second voltage rail via a high-ohmic path.