Apparatus and methods for LNAs with mid-node impedance networks are provided herein. In certain configurations, an LNA includes a mid-node impedance circuit including a resistor and a capacitor electrically connected in parallel, a cascode device electrically connected between an output terminal and the mid-node impedance circuit, and a transconductance device electrically connected between the mid-node impedance circuit and ground. The transconductance device amplifies a radio frequency signal received from an input terminal. The LNA further includes a feedback bias circuit electrically connected between the output terminal and the input terminal and operable to control an input bias voltage of the transconductance device.

An RF amplifier for implementation in SiGe HBT technology is described. The RF amplifier has a cascode stage comprising a common base (CB) transistor and a common emitter (CE) transistor arranged in series between a first voltage rail and a second voltage rail. An RF input is coupled to the base of the CE transistor and an RF output is coupled to the collector of the CB transistor. The RF amplifier includes a CB power-down circuit arranged between the base of the CB transistor and the second voltage rail and a CE power-down circuit arranged between the base of the CE transistor and the second voltage rail. In a power-down mode the CE power-down circuit couples the base of the common-emitter-transistor to the second voltage rail. The CB power-down mode circuit couples the base of the CB transistor to the second voltage rail via a high-ohmic path.

Provided are embodiments that include a circuit configured to operate in a disabled mode error reduction for high-voltage bilateral operational amplifier current source. The circuit includes an operational amplifier, and a switching circuit coupled to the operation amplifier, wherein the switching circuit is operable in a normal mode and a disabled mode, wherein the disabled mode reduces error current at the output of the operational amplifier. Also provided are embodiments for a method for operating a circuit in a disabled mode for error reduction.

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

Circuits, devices and methods related to amplification with active gain bypass. In some embodiments, an amplifier can include a first amplification path implemented to amplify a signal, and having a cascode arrangement of a first input transistor and a cascode transistor to provide a first gain for the signal when in a first mode. The amplifier can further include a second amplification path implemented to provide a second gain for the signal while bypassing at least a portion of the first amplification path when in a second mode. The second amplification path can include a cascode arrangement of a second input transistor and the cascode transistor shared with the first amplification path. The amplifier can further include a switch configured to allow routing of the signal through the first amplification path in the first mode or the second amplification path in the second mode.

Apparatus and methods for LNAs with mid-node impedance networks are provided herein. In certain configurations, an LNA includes a mid-node impedance circuit including a resistor and a capacitor electrically connected in parallel, a cascode device electrically connected between an output terminal and the mid-node impedance circuit, and a transconductance device electrically connected between the mid-node impedance circuit and ground. The transconductance device amplifies a radio frequency signal received from an input terminal. The LNA further includes a feedback bias circuit electrically connected between the output terminal and the input terminal and operable to control an input bias voltage of the transconductance device.

A receiver circuit is disclosed. The receiver circuit includes an amplifier configured to generate an RF signal based on a received signal, where the RF signal includes an information signal and a blocker signal modulating an RF carrier frequency. The receiver circuit also includes an RF filter connected to the amplifier, where the RF filter is configured to selectively attenuate the blocker signal.

Provided are embodiments that include a circuit configured to operate in a disabled mode error reduction for high-voltage bilateral operational amplifier current source. The circuit includes an operational amplifier, and a switching circuit coupled to the operation amplifier, wherein the switching circuit is operable in a normal mode and a disabled mode, wherein the disabled mode reduces error current at the output of the operational amplifier. Also provided are embodiments for a method for operating a circuit in a disabled mode for error reduction.

Apparatus and methods for LNAs with mid-node impedance networks are provided herein. In certain configurations, an LNA includes a mid-node impedance circuit including a resistor and a capacitor electrically connected in parallel, a cascode device electrically connected between an output terminal and the mid-node impedance circuit, and a transconductance device electrically connected between the mid-node impedance circuit and ground. The transconductance device amplifies a radio frequency signal received from an input terminal. The LNA further includes a feedback bias circuit electrically connected between the output terminal and the input terminal and operable to control an input bias voltage of the transconductance device.

The present disclosure relates to a switchable power amplification structure including a first power amplifier (PA), a second PA, a front switching structure, and an end switching structure. The front switching structure is coupled to a radio frequency (RF) input port, and the end switching structure is coupled to an antenna port. Herein, the first PA and the second PA are parallel to each other, each of which is coupled between the front switching structure and the first end switching structure. The front switching structure is configured to selectively couple the first PA and the second PA to the RF input port, while the end switching structure is configured to selectively couple the first PA and the second PA to the first antenna port.