Aspects of the disclosure include a front-end module comprising one or more receive ports configured to be coupled to a transceiver, at least one low-noise amplifier configured to be coupled to the one or more receive ports, one or more antenna ports configured to be coupled to one or more respective antennas, and a multiplexer coupled to the one or more receive ports and to the one or more antenna ports, the multiplexer being configured to route a signal received at the one or more antenna ports to a selected receive port of the one or more receive ports.

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

Disclosed is an apparatus comprising means for transmitting a first signal via at least a first switch, a first amplifier, a second switch and a power amplifier, wherein an output of the second switch is connected to a power amplifier path comprising at least the power amplifier, while transmitting the first signal. An input of the first switch and the output of the second switch are switched to switch between transmitting and receiving. A second signal is received via at least the first switch, the first amplifier and the second switch, wherein the output of the second switch is disconnected from the power amplifier path while receiving the second signal.

A circuit arrangement is provided which includes an array of stages for photon counting current to voltage conversion. Each stage includes a tunable operational transconductance amplifier and a feedback network forming a feedback loop of the operational transconductance amplifier. Each stage is configured to provide an output signal as a function of an input signal that is provided to the amplifier input of the operational transconductance amplifier, wherein the input signal comprises one or more current pulses and the output signal comprises one or more voltage pulses. With the tunable operational transconductance amplifier the transconductance of a stage can be tuned so that differences in peaking time and gain are avoided. Furthermore, an imaging device and a method for operating a circuit arrangement are provided.

Circuits and methods for using in parallel amplification and signal combining are described herein. A circuit uses a digitally controlled multistage cascade combiner, a digital phase and drive signal amplifier controller and a digital combiner controller circuit with N parallel signals with constant amplitudes belonging to an alphabet with M discrete values and discrete phases feeding it. The signals resulting from N power amplifiers (PAs) have also constant amplitudes belonging to an alphabet with N discrete values and discrete phases prior to being fed to the multistage combiner. A digital combiner controller circuit generates digital control information to activate, or deactivate, the outputs of the PAs, where a set of digital control signals generated in digital combiner controller are used to control sets of switches, where the signals can be activated at the combiner's inputs, according to their power and phase values. The digital control information ensures that only in-phase signals are combined in the active combiner stage and any difference among the inputs of the combiners is always minimized. Both digital combiner controller and digital drive signal amplifier controller, share information about the signals not to be fed to the multistage combiner, so that PAs drive signals can also be powered off under these circumstances. In provide high efficiency amplification the signal amplifiers employed before the combining stage may be of switched or current source type.

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

A multi-band power amplifier module includes at least one transmission input terminal, at least one power amplifier circuit that receives a first transmission signal and a second transmission signal through the at least one transmission input terminal, a first filter circuit that allows the first transmission signal to pass therethrough, a second filter circuit that allows the second transmission signal to pass therethrough, at least one transmission output terminal through which the first and second transmission signals output from the first and second filter circuits are output, a transmission output switch that outputs each of the first and second transmission signals output from the at least one power amplifier circuit to the first filter circuit or the second filter circuit, and a first tuning circuit that adjusts impedance matching between the at least one power amplifier circuit and the at least one transmission output terminal.

Circuits and methods for using in parallel amplification and signal combining are described herein. A circuit uses a digitally controlled multistage cascade combiner, a digital phase and drive signal amplifier controller and a digital combiner controller circuit with N parallel signals with constant amplitudes belonging to an alphabet with M discrete values and discrete phases feeding it. The signals resulting from N power amplifiers (PAs) have also constant amplitudes belonging to an alphabet with N discrete values and discrete phases prior to being fed to the multistage combiner. A digital combiner controller circuit generates digital control information to activate, or deactivate, the outputs of the PAs, where a set of digital control signals generated in digital combiner controller are used to control sets of switches, where the signals can be activated at the combiner's inputs, according to their power and phase values. The digital control information ensures that only in-phase signals are combined in the active combiner stage and any difference among the inputs of the combiners is always minimized. Both digital combiner controller and digital drive signal amplifier controller, share information about the signals not to be fed to the multistage combiner, so that PAs drive signals can also be powered off under these circumstances. In provide high efficiency amplification the signal amplifiers employed before the combining stage may be of switched or current source type.

According to an embodiment, a semiconductor device includes a radio-frequency amplifier circuit, a first switch, a second switch, and a third switch. The first switch is coupled between a first node and an input end of the radio-frequency amplifier circuit. The second switch is coupled between the first node and an output end of the radio-frequency amplifier circuit. The third switch is coupled between the first node and a reference potential node. A control end of the third switch is coupled to one of the first node and the reference potential node.

A switching circuit comprises a first transistor, a transformer including a first inductor and a second inductor that is co-centric with the first inductor, a first switch, a second switch, a second transistor, a first output, a second output, and coupling circuitry configured to couple the first inductor to the first transistor, a first end of the second inductor, the first switch, and the first output together at a first node, a second end of the second inductor, the second switch, and the second transistor together at a second node, and the second output to the second transistor.