A variable-gain amplifier and a phased array system are provided. A variable-gain amplifier includes a cascode circuit comprising a first amplification transistor and a second amplification transistor array that are cascaded, the second amplification transistor array comprising a plurality of second amplification transistors connected in parallel and configured to output an adjustable current to an output matching network, the first amplification transistor is a common-source transistor, the plurality of second amplification transistors are common-gate transistors, or the cascode circuit is a common-emitter common-base circuit, the first amplification transistor is a common-emitter amplification circuit, and the second amplification transistor array is a common-base amplification circuit. The variable-gain amplifier further including a variable capacitor circuit coupled to the second amplification transistor array and coupled to the output matching network at first nodes.

Methods for operating amplifiers and related devices. In some embodiments, a method for amplifying a signal can include partially amplifying a signal with a common amplification stage. The method can further include providing a bias signal to a selected one of a plurality of dedicated amplification stages each coupled to the common amplification stage and including an output node, such that the selected dedicated amplification stage further amplifies the partially amplified signal and provides the further amplified signal at the respective output node.

A radio-frequency circuit includes a first switch which includes a common terminal, a first selection terminal, and a second selection terminal, and switches between connecting the common terminal and the first selection terminal and connecting the common terminal and the second selection terminal; a first low-noise amplifier including an input terminal connected to the first selection terminal, and a second low-noise amplifier including an input terminal connected to the second selection terminal. The frequency band in which the first low-noise amplifier amplifies a radio-frequency signal by at least a predetermined gain includes the frequency band in which the second low-noise amplifier amplifies a radio-frequency signal by at least a predetermined gain.

Chopper amplifiers with tracking of multiple input offsets are disclosed herein. In certain embodiments, a chopper amplifier includes chopper amplifier circuitry including an input chopping circuit, an amplification circuit, and an output chopping circuit electrically connected along a signal path. The amplification circuit includes two or more pairs of input transistors, from which a control circuit chooses a selected pair of input transistors to amplify an input signal. The chopper amplifier further incudes an offset correction circuit that senses the signal path to generate an input offset compensation signal for the amplification circuit. Furthermore, the offset correction circuit separately tracks an input offset of each of the two or more pairs of input transistors.

A differential amplifier is provided. The differential amplifier includes a first load, a second load, a current source, a differential pair circuit, a first and a second switch circuit. The differential pair circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first switch circuit controls the first and the second transistors, and the second switch circuit controls the third and the fourth transistors. Through the control and selection of the first and second switch circuits, a differential pair is selected in the differential pair circuit to receive and process a first input signal and a second input signal for signal.

A receiver circuit is disclosed. The receiver circuit includes an amplifier configured to generate an RF signal based on a received signal, where the RF signal includes an information signal and a blocker signal modulating an RF carrier frequency. The receiver circuit also includes an RF filter connected to the amplifier, where the RF filter is configured to selectively attenuate the blocker signal.

In electronic circuits having various gain states, small gain phase shift differences required among various gain states may pose a challenging problem. The disclosed methods and devices provide solution to such challenge. Electronic circuits are described wherein a first path including an amplifier may be bypassed by a second path including only passive elements and for gain states smaller than 0 dB. In such electronic circuits, a phase shifter included in the second path can be adjusted to address the required phase shift among various gain states.

Method of operating a power combiner network (1), the power combiner network (1) comprising a power combiner device (10) having N secondary ports (11(1, 2, N)) combining into one primary port (12), wherein respective N secondary port (11(1, 2, . . . , N)) is provided with a phase shifter arrangement (13) and a load control arrangement (14). Respective phase shifter arrangement (13) is configured to set a phase of a signal fed through respective N secondary port (11(1, 2, . . . , N)). Respective load control arrangement (14) is configured to set the N secondary ports (11(1, 2, . . . , N)) in an active or in an inactive operation mode. For I inactive secondary ports (11(1)) the load control arrangement (14) is further configured to set a phase of the signal reflected from the I inactive secondary ports (11(1)). The method comprises the method steps of; step A (100), selecting which of the N secondary ports (11(1, 2, . . . , N)) that should be set in an inactive operation mode and which of the N secondary ports (11(1, 2, . . . , N)) that should be set in an active operation mode, step B (110), setting selected I inactive secondary ports (11(1)) in an inactive operation mode by means of the load control arrangement (14), step C (120), retrieving a phase required for respective I inactive secondary port (11(1)) and retrieving a phase required for respective A active secondary port (11(2)) in order for respective A active secondary port (11(2)) to minimize the reflected signal from the power combiner device (10) and provide desired power to the primary port (12), step D (130), setting respective load control arrangement (14) for respective I inactive secondary port (11(1)) according to respective retrieved phase, and step E (140), setting respective phase shifter arrangement (13) for respective A active secondary port (11(2)) according to respective retrieved phase.

An amplifier circuit includes an output terminal, an amplification unit and a switch. The output terminal is used to output an amplification signal. The amplification unit includes a first transistor and a second transistor. The first transistor includes a control terminal for receiving a first input signal, a first terminal coupled to the output terminal for outputting an amplified first input signal, and a second terminal. The second transistor includes a control terminal for receiving a second input signal, a first terminal coupled to the output terminal for outputting an amplified second input signal, and a second terminal. The switch includes a first terminal coupled to the second terminal of the first transistor, and a second terminal. The amplification signal is generated using at least the amplified first input signal and/or the amplified second input signal.

The present disclosure relates to a switchable power amplification structure including a first power amplifier (PA), a second PA, a front switching structure, and an end switching structure. The front switching structure is coupled to a radio frequency (RF) input port, and the end switching structure is coupled to an antenna port. Herein, the first PA and the second PA are parallel to each other, each of which is coupled between the front switching structure and the first end switching structure. The front switching structure is configured to selectively couple the first PA and the second PA to the RF input port, while the end switching structure is configured to selectively couple the first PA and the second PA to the first antenna port.