A method for simple measurement of phase shift between a first clock signal and a second clock signal is described, each clock signal having a period T.sub.0. The method includes: feeding the first clock signal into a first input of a mixer; feeding the second clock signal into a second input of the mixer; feeding the output signal of the mixer into a low pass filter; and measuring the output signal of the low pass filter, with the aid of an output voltage that is normalized to operating voltage of the mixer. A circuit for implementing the method includes a mixer and a low pass filter. The mixer includes a first input for feeding in the first clock signal, and a second input for feeding in the second clock signal. The output of the mixer is connected to the input of the low pass filter.

A communication device is provided. The communication device includes: an antenna; a matching circuit connected with the antenna; a transmitter configured to generate a transmission communication signal and provide the transmission communication signal to the antenna through the matching circuit; a filter connected between the matching circuit and the antenna; and a receiver configured to receive an attenuated signal from the antenna through the filter. The filter is configured to pass frequencies of an antenna signal corresponding to a pass band and attenuate frequencies of the antenna signal corresponding to a stop band, and a center frequency of the transmission communication signal corresponds to the stop band of the filter.

A communication device is provided. The communication device includes: an antenna; a matching circuit connected with the antenna; a transmitter configured to generate a transmission communication signal and provide the transmission communication signal to the antenna through the matching circuit; a filter connected between the matching circuit and the antenna; and a receiver configured to receive an attenuated signal from the antenna through the filter. The filter is configured to pass frequencies of an antenna signal corresponding to a pass band and attenuate frequencies of the antenna signal corresponding to a stop band, and a center frequency of the transmission communication signal corresponds to the stop band of the filter.

The disclosure provides methods of synthesizing DNA using topoisomerase-mediated ligation, by adding single nucleotides or oligomers to a DNA strand in the 3′ to 5′ direction.

An integrated circuit including a first circuit module and a second circuit module is provided. A layer stack may include one or multiple metal layers with a power segment and a ground segment connected to the first circuit module and the second circuit module, which form a resonant current loop. A pickup loop may be inductively coupled to the resonant current loop to dampen its resonance, thereby making the IC compliant with its EMC requirements or removing functional errors such as problems in the signal or power integrity.

A multi-port coupled inductor with interference suppression is provided with a first signal port connected to a first resistor port via a first inductor; a second resistor port connected to the first resistor port via a second inductor; a second signal port connected to the second resistor port via a third inductor; a third resistor port connected to the first resistor port via a first resistor; a fourth resistor port connected to the third resistor port via a fourth inductor and to the second resistor port via a second resistor; a third signal port connected to the third resistor port via a fifth inductor; and a fourth signal port connected to the fourth resistor port via a sixth inductor.

A multi-port coupled inductor with interference suppression is provided with a first signal port connected to a first resistor port via a first inductor; a second resistor port connected to the first resistor port via a second inductor; a second signal port connected to the second resistor port via a third inductor; a third resistor port connected to the first resistor port via a first resistor; a fourth resistor port connected to the third resistor port via a fourth inductor and to the second resistor port via a second resistor; a third signal port connected to the third resistor port via a fifth inductor; and a fourth signal port connected to the fourth resistor port via a sixth inductor.

An electronic device has a substrate and first and second metallization levels with a resonant circuit. The first metallization level has a first dielectric layer on a side of the substrate, and a first metal layer on the first dielectric layer. The second metallization level has a second dielectric layer on the first dielectric layer and the first metal layer, and a second metal layer on the second dielectric layer. The electronic device includes a first plate in the first metal layer, and a second plate spaced apart from the first plate in the second metal layer to form a capacitor. The electronic device includes a winding in one of the first or second metal layers and coupled to one of the first or second plates in a resonant circuit.

A bias circuit includes first to fourth transistors and a phase compensation circuit. In the first transistor, a reference current or voltage is supplied to a first terminal, and the first terminal and a second terminal are connected. In the second transistor, a first terminal is connected to the first transistor, and a third terminal is grounded. In the third transistor, a power supply voltage is supplied to a first terminal, a second terminal is connected to the first transistor, and a bias current or voltage is supplied from a third terminal to an amplifier transistor. In the fourth transistor, a first terminal is connected to the third transistor, a second terminal is connected to the second transistor, and a third terminal is grounded. The phase compensation circuit is provided in a path extending from the fourth transistor to the third transistor through the second and first transistors.

A bias circuit includes first to fourth transistors and a phase compensation circuit. In the first transistor, a reference current or voltage is supplied to a first terminal, and the first terminal and a second terminal are connected. In the second transistor, a first terminal is connected to the first transistor, and a third terminal is grounded. In the third transistor, a power supply voltage is supplied to a first terminal, a second terminal is connected to the first transistor, and a bias current or voltage is supplied from a third terminal to an amplifier transistor. In the fourth transistor, a first terminal is connected to the third transistor, a second terminal is connected to the second transistor, and a third terminal is grounded. The phase compensation circuit is provided in a path extending from the fourth transistor to the third transistor through the second and first transistors.