A multilayer fringe capacitor includes first and second interdigitated capacitor electrodes, both parallel to and intersecting a first planar surface; third and fourth interdigitated capacitor electrodes, the first and second electrodes parallel to and separated by a non-zero distance from the third and fourth electrodes; a first set of coupling vias that electrically couples the first electrode to the third electrode; and a second set of coupling vias that electrically couples the second electrode to the fourth electrode.

An apparatus for monitoring radio frequency (RF) signals is disclosed. The apparatus includes an RF splitter, a set of track-and-hold circuits, a set of analog-to-digital circuits (ADC) and a frequency tracking module. The RF splitter splits a set of incoming RF signals into multiple RF signal paths. Each of the track-and-hold circuits, which is clocked at a different frequency than others, samples the incoming RF signals from a respective one of the RF signal paths. Each of the ADCs receives the sampled data from a respective one of the track-and-hold circuits. Each of the ADCs is also clocked at same frequency as a corresponding one of the track-and-hold circuits. The frequency tracking module determines a frequency of the incoming RF signals.

In some examples, a delay apparatus includes a controllable delay line comprising a plurality of delay elements selectively connected in a signal path to vary a delay of a signal passing through the delay line, and a controllable phase shifter comprising reflective loads adjustable to vary a phase shift applied to the signal.

An analog time delay filter circuit including a first delay circuit block arranged in a modular layout, having a first time delay filter, a first input, a first output, and first and second pass-throughs; and a second delay circuit block arranged in the same modular layout, having a second time delay filter, a second input, a second output, and third and fourth pass-throughs.

An analog time delay filter circuit including a first delay circuit block arranged in a modular layout, having a first time delay filter, a first input, a first output, and first and second pass-throughs; and a second delay circuit block arranged in the same modular layout, having a second time delay filter, a second input, a second output, and third and fourth pass-throughs.

A time delay filter comprising a substrate; four coupled LC resonators, each having a coupling point; a first capacitor that electrically couples the first coupling point to the second coupling point; a second capacitor that electrically couples the second coupling point to the third coupling point; and a third capacitor that electrically couples the third coupling point to the fourth coupling point; the filter group delaying a signal output at the fourth coupling point relative to a signal input at the first coupling point.

A time delay filter comprising a substrate; four coupled LC resonators, each having a coupling point; a first capacitor that electrically couples the first coupling point to the second coupling point; a second capacitor that electrically couples the second coupling point to the third coupling point; and a third capacitor that electrically couples the third coupling point to the fourth coupling point; the filter group delaying a signal output at the fourth coupling point relative to a signal input at the first coupling point.

According to an embodiment, a radio frequency delay line is described comprising a first conductor comprising a plurality of first inductors, a second conductor comprising a plurality of second inductors, wherein each of the plurality first inductors corresponds to a respective one of the plurality of second inductors and a plurality of inductor pairs, each inductor pair comprising a first inductor and the corresponding second inductor. For each of the plurality of inductor pairs, the first inductor and the corresponding second inductor are arranged so that an inductor area of the first inductor overlaps with an inductor area of the corresponding second inductor.

An accessory device, configured to be interfaced with a master device, and configured to operate in an analog mode and in a digital mode, the accessory device including: a startup circuit including: a first transistor that interfaces the accessory device to the master device, wherein the first transistor is configured with a first resistive capacitive (RC) circuit to turn on the first transistor according to a time constant of the first RC circuit; a second transistor coupled between ground and the first RC circuit, wherein the second transistor is configured to control a gate of the first transistor in response to a control signal; and a diode having an anode coupled to the first node and a cathode coupled to a body terminal of the first transistor.

An accessory device, configured to be interfaced with a master device, and configured to operate in an analog mode and in a digital mode, the accessory device including: a startup circuit including: a first transistor that interfaces the accessory device to the master device, wherein the first transistor is configured with a first resistive capacitive (RC) circuit to turn on the first transistor according to a time constant of the first RC circuit; a second transistor coupled between ground and the first RC circuit, wherein the second transistor is configured to control a gate of the first transistor in response to a control signal; and a diode having an anode coupled to the first node and a cathode coupled to a body terminal of the first transistor.