A first switch is connected in parallel with a circuit element. A second switch is connected in series with a parallel circuit constituted by the circuit element and the first switch. The first switch and the second switch alternately perform on-off operation.

A first switch is connected in parallel with a circuit element. A second switch is connected in series with a parallel circuit constituted by the circuit element and the first switch. The first switch and the second switch alternately perform on-off operation.

A hybrid coupler operating in a power divider mode includes two inputs, two outputs, a capacitive module coupled between the inputs and the outputs or on each input and each output. The capacitive module has an adjustable capacitive value making it possible to adjust the central frequency. A calibration method includes: delivering a first reference signal having a first reference frequency on the first input of the hybrid coupler, measuring the peak value of a first signal delivered to the first output of the coupler and measuring the peak value of a second signal delivered to the second output of the coupler. The two peak values are compared and an adjustment of the capacitive value of the capacitive module is made until an equality of the peak values is obtained to within a tolerance.

A hybrid coupler operating in a power divider mode includes two inputs, two outputs, a capacitive module coupled between the inputs and the outputs or on each input and each output. The capacitive module has an adjustable capacitive value making it possible to adjust the central frequency. A calibration method includes: delivering a first reference signal having a first reference frequency on the first input of the hybrid coupler, measuring the peak value of a first signal delivered to the first output of the coupler and measuring the peak value of a second signal delivered to the second output of the coupler. The two peak values are compared and an adjustment of the capacitive value of the capacitive module is made until an equality of the peak values is obtained to within a tolerance.

Switch circuits for electrical power are formed of a hybrid coupler configured to receive a signal as an input, and output first and second pulsed wave signals along first and second signal paths, respectively; in a plurality of time frames, wherein the phases of the first and second pulsed wave signals along first and second signal paths are aligned. The switch circuits may be incorporated in time folding power circuits as an exemplary application.

Switch circuits for electrical power are formed of a hybrid coupler configured to receive a signal as an input, and output first and second pulsed wave signals along first and second signal paths, respectively; in a plurality of time frames, wherein the phases of the first and second pulsed wave signals along first and second signal paths are aligned. The switch circuits may be incorporated in time folding power circuits as an exemplary application.

A host interface includes; a phase shift detector, a phases shifter, and control logic controlling operation of the phase shift detector and the phase shifter. The host interface sends a command and a clock to a device, receives a response from the device, communicates data to the device synchronously with the clock, and samples data received from the device synchronously with a modulated clock. The phase shift detector provides a shift value based on the response, and the phase shifter modulates a phase of the clock based on the shift value to generate the modulated clock.

A host interface includes; a phase shift detector, a phases shifter, and control logic controlling operation of the phase shift detector and the phase shifter. The host interface sends a command and a clock to a device, receives a response from the device, communicates data to the device synchronously with the clock, and samples data received from the device synchronously with a modulated clock. The phase shift detector provides a shift value based on the response, and the phase shifter modulates a phase of the clock based on the shift value to generate the modulated clock.

A phase shifter includes: a first transistor including a first source and a first drain; a second transistor including a second source and a second drain; a first inductor connected with the first source and the first drain, connected in parallel with the first transistor, and including a first body part having an interrupted part, and a first connection part formed at the interrupted part; a second inductor connected with the second source and the second drain, connected in parallel with the second transistor, and including a second body part having an interrupted part, and a second connection part formed at the interrupted part; an inspection drain terminal connected with the first drain and the second drain; and an inspection source terminal connected with the first source and the second source.

A phase shifter includes: a first transistor including a first source and a first drain; a second transistor including a second source and a second drain; a first inductor connected with the first source and the first drain, connected in parallel with the first transistor, and including a first body part having an interrupted part, and a first connection part formed at the interrupted part; a second inductor connected with the second source and the second drain, connected in parallel with the second transistor, and including a second body part having an interrupted part, and a second connection part formed at the interrupted part; an inspection drain terminal connected with the first drain and the second drain; and an inspection source terminal connected with the first source and the second source.