A phase detector includes: a phase shift circuit to phase-shift a first positive-phase signal included in a first differential signal and a first negative-phase signal included in the first differential signal, and phase-shift a second positive-phase signal included in a second differential signal and a second negative-phase signal included in the second differential signal; a multiplication circuit to perform multiplication of two signals for all combinations of the first positive-phase signal and the first negative-phase signal with the phase-shifted second positive-phase signal and the phase-shifted second negative-phase signal, and perform multiplication of two signals for all combinations of the phase-shifted first positive-phase signal and the phase-shifted first negative-phase signal with the second positive-phase signal and the second negative-phase signal; and a phase difference calculating circuit to calculate a phase difference between the first differential signal and the second differential signal using multiplication signals of the multiplication circuit.

A phase detector includes: a phase shift circuit to phase-shift a first positive-phase signal included in a first differential signal and a first negative-phase signal included in the first differential signal, and phase-shift a second positive-phase signal included in a second differential signal and a second negative-phase signal included in the second differential signal; a multiplication circuit to perform multiplication of two signals for all combinations of the first positive-phase signal and the first negative-phase signal with the phase-shifted second positive-phase signal and the phase-shifted second negative-phase signal, and perform multiplication of two signals for all combinations of the phase-shifted first positive-phase signal and the phase-shifted first negative-phase signal with the second positive-phase signal and the second negative-phase signal; and a phase difference calculating circuit to calculate a phase difference between the first differential signal and the second differential signal using multiplication signals of the multiplication circuit.

In an embodiment, a method for determining the phase shift between a first signal and a second signal includes: delivering the first signal to a first input of a 90° hybrid coupler; delivering the second signal to a second input of the 90° hybrid coupler; determining a first piece of information relating to a power of a first output signal delivered to a first output of the 90° hybrid coupler; determining a second piece of information relating to a power of a second output signal delivered to a second output of the coupler; and adjusting the phase of the second signal until obtaining a calibrated phase for which the first piece of information is substantially equal to the second piece of information, wherein the first and second signals have identical frequencies, and wherein the phase shift between the first signal and the second signal is equal to the calibrated phase.

In an embodiment, a method for determining the phase shift between a first signal and a second signal includes: delivering the first signal to a first input of a 90° hybrid coupler; delivering the second signal to a second input of the 90° hybrid coupler; determining a first piece of information relating to a power of a first output signal delivered to a first output of the 90° hybrid coupler; determining a second piece of information relating to a power of a second output signal delivered to a second output of the coupler; and adjusting the phase of the second signal until obtaining a calibrated phase for which the first piece of information is substantially equal to the second piece of information, wherein the first and second signals have identical frequencies, and wherein the phase shift between the first signal and the second signal is equal to the calibrated phase.

The present application relates to a method and apparatus for implementing a radar array including a gate bias source for providing a first variable voltage, a back gate well control for providing a second variable voltage, and a field effect transistor having a drain, a source, a gate and a back gate well control, the field effect transistor being further configured to couple an alternating current radar signal between the drain and the source and to adjust a phase of the alternating current radar in response to first variable voltage applied to the gate and the second variable voltage applied to the back gate well control.

The present application relates to a method and apparatus for implementing a radar array including a gate bias source for providing a first variable voltage, a back gate well control for providing a second variable voltage, and a field effect transistor having a drain, a source, a gate and a back gate well control, the field effect transistor being further configured to couple an alternating current radar signal between the drain and the source and to adjust a phase of the alternating current radar in response to first variable voltage applied to the gate and the second variable voltage applied to the back gate well control.

Phase shifters such as networks that can be used in MMIC (Monolithic Microwave Integrated Circuit) and hybrid digital phase shifters, for low loss, wide bandwidth, and high linearity. A digital phase shifter includes input port for receiving signals and output ports for transmitting the signals. Multiple transmission lines are arranged between the input and output ports of the phase shifter. The transmission lines are arranged in a ring with first pair of the transmission lines which are arranged in series in a first path and second pair of the transmission lines arranged in series in a second path. One of the transmission lines of the first and second pairs include quarter-wave hybrid coupled line with coupled-ports and through-ports terminated in short-circuit. Hybrid coupled line can be a Lange coupler with or without RF crossover.

Phase shifters such as networks that can be used in MMIC (Monolithic Microwave Integrated Circuit) and hybrid digital phase shifters, for low loss, wide bandwidth, and high linearity. A digital phase shifter includes input port for receiving signals and output ports for transmitting the signals. Multiple transmission lines are arranged between the input and output ports of the phase shifter. The transmission lines are arranged in a ring with first pair of the transmission lines which are arranged in series in a first path and second pair of the transmission lines arranged in series in a second path. One of the transmission lines of the first and second pairs include quarter-wave hybrid coupled line with coupled-ports and through-ports terminated in short-circuit. Hybrid coupled line can be a Lange coupler with or without RF crossover.

An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes. At least one of the plurality of clock generation circuits is an active circuit, and at least one of the plurality of clock generation circuits is a passive circuit.

A phase rotator control circuit is provided. The phase rotator control circuit is coupled to a phase rotator core and includes a first set of transistors coupled to receive digital control signals. The first set of transistors is coupled to a second set of transistors configured and arranged to form a filtered current mirror. An output of the filtered current mirror is coupled to provide an analog phase control signal to the phase rotator core.