An apparatus and method are provided for controlling a delay circuit. Included is a delay circuit configured to receive a probe signal. Further provided is a controller in electrical communication with the delay circuit. The controller is configured to perform various operations, in response to the receipt of the probe signal by the delay circuit. A positive peak and a negative peak of an output of the delay circuit are measured. Further, a ratio involving the positive peak and the negative peak of the output of the delay circuit is calculated. A delay of the delay circuit is controlled, based on the ratio.

A delay circuit includes precharge and discharge transistors configured to receive an input signal. The delay circuit also includes a resistor coupled to the precharge transistor having a negative temperature coefficient to thereby form a node. A capacitive device and an inverter are coupled to the node. The inverter produces an output signal. Responsive to the input signal having a first polarity, the precharge transistor is configured to be turned on and the discharge transistor is configured to be turned off to thereby cause current to flow through the precharge transistor to the capacitive device to thereby charge the capacitive device. Responsive to the input signal having a second polarity, the precharge and discharge transistors are configured to change state to thereby cause charge from the capacitive device to discharge through the resistor and through the discharge transistor. The voltage on the node decays to a level which eventually causes the inverter's output to change state.

A PVTM-based wide voltage range clock stretching circuit is disclosed. The circuit consists of a PVTM circuit module, a phase clock generation module, a clock synchronization selection module and a control module. The PVTM circuit module monitors in real time the delay information of an on-chip delay unit to monitor the operating environment of the circuit, and feeds the delay information back to the control module. Under the control of a clock stretching enable signal and a clock stretching extent signal, the control module selects a target phase clock from the clocks generated by the phase clock generation module in accordance with the feedback from the PVTM, enabling the stretching of system clock within a single cycle in different PVT conditions. Sophisticated gate devices are not required, and the cost of area and power consumption are kept to minimal.

Methods, systems, and apparatuses, including computer programs encoded on computer-readable media, for a microwave cavity resonator stabilized oscillator, are described. The oscillator can include a cavity resonator configured to resonate at least at one predetermined resonant frequency in a GHz frequency range. The oscillator can include circuitry including a microwave amplifier, a low pass filter and a phase shifter. The circuitry may be arranged in a feedback loop configuration, and may be at least partially mounted above a first surface of the cavity resonator. The circuitry may be electrically coupled to the cavity resonator to form an oscillator. The circuitry can include a first delay line segment that is selected instead of at least one other delay line segments for wire-bond connection to complete the feedback loop configuration at zero degree phase.

A semiconductor system includes: a controller suitable for outputting an external clock signal and a command/address signal; and a semiconductor device suitable for selecting one of pre-stored code values of a delay control signal to output an initial value control signal according to the command/address signal, and outputting an internal clock signal by delaying the external clock signal by a predetermined time based on the delay control signal having an initial value that is set in response to the initial value control signal.

A tunable analog noise-cancelling transversal reconfigurable filter for filtering an RF signal. The filter includes a noise-cancelling balun responsive to the RF signal and providing gain and noise suppression, and a time delay network responsive to the signal from the balun. The time delay network includes a single continuous three-dimensional air coaxial line where a separate tap is provided between sections of the line. The filter also includes a multiplication and summing network having a plurality of multiplication stages, where each stage is fed by a voltage signal from at least one of the taps, and each stage includes a multiplication amplifier that amplifies the voltage signal. A tuning element provides a multiplication coefficient to the amplified signal. Each amplified signal in each stage is added on an output line, where the multiplication and summing network operates under Millman's Theorem.

A data stream processing device including a first tapped delay line which outputs data values received via a first data input on N first taps, wherein N is two or more; a second tapped data delay line which outputs data values received via a second data input on N second taps; a first processing unit including N first delayed data inputs and which generates a first data output based on the N first delayed data inputs; a second processing unit including N second delayed data inputs and which generates a second data output based on the N second delayed data inputs; and control circuitry including a mode selection input, and which is coupled to in response to the mode selection input receiving a signal indicating a first mode, simultaneously couple each of the first taps to a respective one of the first delayed data inputs and couple each of the second taps to a respective one of the second delayed data inputs, and in response to the mode select input not receiving a signal indicating the first mode, simultaneously couple one of the first taps to one of the second delayed data inputs and couple one of the second taps to one of the first data inputs.

A data stream processing device including a first tapped delay line which outputs data values received via a first data input on N first taps, wherein N is two or more; a second tapped data delay line which outputs data values received via a second data input on N second taps; a first processing unit including N first delayed data inputs and which generates a first data output based on the N first delayed data inputs; a second processing unit including N second delayed data inputs and which generates a second data output based on the N second delayed data inputs; and control circuitry including a mode selection input, and which is coupled to in response to the mode selection input receiving a signal indicating a first mode, simultaneously couple each of the first taps to a respective one of the first delayed data inputs and couple each of the second taps to a respective one of the second delayed data inputs, and in response to the mode select input not receiving a signal indicating the first mode, simultaneously couple one of the first taps to one of the second delayed data inputs and couple one of the second taps to one of the first data inputs.

A circuit device includes a first circuit, a second circuit, and a comparator array section. The first circuit has a first DLL circuit having a plurality of delay elements, and delays a first signal. The second circuit has a second DLL circuit having a plurality of delay elements, and delays a second signal. The comparator array section has a plurality of phase comparators arranged in a matrix, the first delayed signal group from the first circuit and the second delayed signal group from the second circuit are input to the comparator array section, and the comparator array section outputs a digital signal corresponding to a time difference in the transition timing between the first signal and the second signal.

A circuit device includes a first circuit, a second circuit, and a comparator array section. The first circuit has a first DLL circuit having a plurality of delay elements, and delays a first signal. The second circuit has a second DLL circuit having a plurality of delay elements, and delays a second signal. The comparator array section has a plurality of phase comparators arranged in a matrix, the first delayed signal group from the first circuit and the second delayed signal group from the second circuit are input to the comparator array section, and the comparator array section outputs a digital signal corresponding to a time difference in the transition timing between the first signal and the second signal.