A current control circuit and a bias generator including the current control circuit are provided. The bias generator may include a current mirror circuit configured to generate one of a first current and a second current based on a reference current; a switch circuit configured to transfer one of the first current and the second current to a variable resistor; an operational amplifier including a first input node connected to the switch circuit, a second input node that receives a reference voltage, and an output node that outputs a bias voltage; and the variable resistor connected between the first input node and the output node of the operational amplifier. By switching operation of the switch circuit, a direction in which the first current flows in the variable resistor may be different from a direction in which the second current flows in the variable resistor.

A phase shifter for altering the phase of a radio frequency signal is disclosed herein. A Lange coupler is used having reflective ports that are coupled to artificial transmission lines. The artificial transmission lines provide a reflection transmission path, the length of which can be determined by digital control lines. Transistors placed along the length of the central trace provide independent paths to ground that serve to shorten the electrical length of the ATL. Accordingly, by selectively turning the transistors on/off, the electrical length of the ATL can be selected and thus the amount of phase delay introduced by the phase shifter.

Systems, methods and devices are disclosed for a variable-rate true-time delay (VR-TTD) decimator for receiving an input data signal and providing an output decimated signal. The VR-TTD decimator may comprise: a VR-TTD decimator input for receiving the input data signal; and a VR-TTD decimator output for outputting the output decimated signal; a numerically controlled oscillator (NCO) for receiving a time delay control signal and a desired rate signal and for controlling coarse filtering, fine filtering and decimation of the input data signal; and an accumulator for generating the output decimated signal, wherein the accumulator comprises a plurality of shift registers, controlled by the NCO. The system may comprise a beamformer for providing an output signal coherently summed from a plurality of paths, where each path comprises a VR-TTD decimator for providing VR-TTD to the respective signals of the plurality of paths.

Systems, methods and devices are disclosed for a variable-rate true-time delay (VR-TTD) decimator for receiving an input data signal and providing an output decimated signal. The VR-TTD decimator may comprise: a VR-TTD decimator input for receiving the input data signal; and a VR-TTD decimator output for outputting the output decimated signal; a numerically controlled oscillator (NCO) for receiving a time delay control signal and a desired rate signal and for controlling coarse filtering, fine filtering and decimation of the input data signal; and an accumulator for generating the output decimated signal, wherein the accumulator comprises a plurality of shift registers, controlled by the NCO. The system may comprise a beamformer for providing an output signal coherently summed from a plurality of paths, where each path comprises a VR-TTD decimator for providing VR-TTD to the respective signals of the plurality of paths.

A delay line device is provided for a high frequency sampler for high frequency signal transmission, or for an oscilloscope for measuring high frequency signals. The delay line device includes two distributed tapped transmission delay lines. Each of the delay lines includes two terminals. An analog input signal is applied to a first terminal of the first delay line, and a clock signal is applied to a first terminal of the second delay line. The delay lines are configured such that the analog input signal propagates through the first delay line in an opposite direction as compared to the propagation of the clock signal through the second delay line.

Clock generation circuits including a single and multi-phase clock circuits are disclosed. A clock generation circuit is coupled to receive a first pulse on a first input and a second pulse on a second input. The first pulse may be generated responsive to a rising edge of an input clock signal, while the second pulse may be generated responsive to a falling edge of the input clock signal. Responsive to the first pulse, an output node of the clock generation circuit may be pulled high. Responsive to the second pulse, the output node may be pulled low. During those points in which neither pulse is asserted, a state element in the clock generation circuit may hold the output node to its most recent value. Using delay elements and multiple instances of the clock generation circuit and pulse generation circuits, a multi-phase clock generation circuit may be constructed.

A delay circuit is provided. The delay circuit includes a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay circuit. Furthermore, the delay circuit is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge an input signal being actively delayed by the delay circuit when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.

A delay line circuit includes a plurality of delay circuits and a variable delay line circuit. The plurality of delay circuits receives an input signal and to generate a first output signal. The first output signal corresponds to a delayed input signal or an inverted input signal. The variable delay line circuit receives the first output signal. The variable delay line circuit includes an input end, an output end, a first and a second path. The input end is configured to receive the first output signal. The output end is configured to output a second output signal. The first path includes a first plurality of inverters and a first circuit. The second path includes a second plurality of inverters and a second circuit. The received first output signal is selectively transmitted through the first or second path based on a control signal received from a delay line controller.

Embodiments relate to modulating a power supply voltage for varying a propagation delay of data paths within an integrated circuit. The power supply voltage is modulated to increase the delay of shorter data paths for reducing an incidence of hold time violations without substantially affecting the delay of longer data paths. For example, the power supply voltage is reduced from a nominal value in the first half clock cycle to increase delay of both the shorter data paths and the longer data paths. The power supply voltage is increased from the nominal value in the second half clock cycle to decrease delay of the longer data paths within the second half clock cycle such that the overall delay of the longer data paths is virtually same as when the power supply voltage is fixed at the nominal value for the entire clock cycle.

An example of the invention provides a digital delay unit that is made up of a plurality of NAND gates. The digital delay unit includes a first delay path and a second delay path. The first delay path is coupled between a first input terminal and an output terminal to provide a basic time delay which is caused by one NAND gate. The second delay path is coupled between a second input terminal and the output terminal to provide at least three basic time delays.