A resonator circuit has first to sixth transconductance units and the first to fourth connectors. The first transconductance unit has the first top, bottom, and control terminals. The second transconductance unit has the second top terminal connected to the first bottom terminal and has the second bottom and control terminals. The third transconductance unit has a third top terminal connected to the first top terminal and has the third bottom and control terminals. The fourth transconductance unit has the fourth top, bottom, and control terminals. The fifth transconductance unit has the fifth top terminal connected to the fourth bottom terminal and has the fifth bottom and control terminals. The sixth transconductance unit has the sixth top terminal connected to the fourth top terminal and has the sixth bottom and control terminals.

An oscillator circuit includes a bulk acoustic wave resonator, a differential active inductor circuit, and a gain circuit. The differential active inductor circuit is configured to bias the bulk acoustic wave resonator. The differential active inductor circuit is coupled between the bulk acoustic wave resonator and a power supply terminal. The gain circuit is coupled to the bulk acoustic wave resonator.

A tunable impedance simulator and impedance multiplier circuit and a system for configuring a second generation voltage-mode conveyor circuit (VCII) as the tunable impedance simulator and impedance multiplier are described. The tunable impedance simulator and impedance multiplier circuit includes one VCII having a positive input terminal connected to a voltage source, a negative input terminal connected to the voltage source, and an impedance terminal Z.sub.0 . The impedance terminal Z.sub.0 can be either positive or negative. When the impedance terminal Z.sub.0 is positive, a positive active inductor, a positive capacitance multiplier, and a positive resistance multiplier may be implemented. When the impedance terminal Z.sub.0 is negative, a negative active inductor, a negative capacitance simulator, and a negative resistance simulator may be implemented.

The present invention relates to a capacitance multiplier topology suitable for both positive and negative capacitance multiplication having a minimum configuration consisting of a current feedback amplifier (CFOA), two resistors and a reference capacitor, with each C-multiplier having a respective capacitance amplification constant k which is externally adjustable. Such a capacitance multiplier has less parasitic components, occupies a smaller chip area with higher simulated capacitance value.

An electronic emulation component for actively emulating a passive electronic component such as a capacitor or inductor having a desired value, comprises a pair of terminals for connection to an external circuit and across which the desired value is to appear, a power convertor, and a passive electronic component of the type to be emulated but having a value different from the value to be emulated and isolated from the pair of terminals by the convertor.

An electronic emulation component for actively emulating a passive electronic component such as a capacitor or inductor having a desired value, comprises a pair of terminals for connection to an external circuit and across which the desired value is to appear, a power convertor, and a passive electronic component of the type to be emulated but having a value different from the value to be emulated and isolated from the pair of terminals by the convertor.

A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier

A method of and an apparatus for reducing noise in a non-Foster circuit having at least a pair of cross coupled transistor devices, each transistor device of the pair of cross coupled transistor devices having a pair of current carrying electrodes. The method and apparatus involves coupling inductors with each pair of the current carrying electrodes of each of the cross-coupled transistor devices in the non-Foster circuit, the inductors also being coupled with voltage and/or current sources associated with or coupled to the non-Foster circuit. The nominal values of the inductors are selected to provide a load asymmetry, so that the load inductor in the input side of the non-Foster circuit has a larger inductance than the load inductor at the output side of non-Foster circuit.

A radio frequency integrated circuit includes an amplification circuit for outputting a radio frequency signal to an antenna, a balun including a first terminal, a second terminal, a third terminal, and a fourth terminal, and a variable capacitance circuit including a fifth terminal and a sixth terminal. The first terminal and the second terminal of the balun receive output signals of the amplification circuit. The third terminal and the fourth terminal of the balun are connected to the fifth terminal and the sixth terminal of the variable capacitance circuit, respectively, and the fifth terminal is connected to a radio frequency output terminal. The variable capacitance circuit includes a plurality of capacity cells that are connected in parallel between two output terminals.

A circuit for controlling a capacitor having a capacitance adjustable by biasing, including an amplifier for delivering a D.C. bias voltage, having a feedback slowed down by a resistive and capacitive cell.