An element which oscillates or detects terahertz waves includes a resonance unit including a differential negative resistance element, a first conductor, a second conductor, and a dielectric body, a bias circuit configured to supply a bias voltage to the differential negative resistance element, and a line configured to connect the resonance unit and the bias circuit to each other. The differential negative resistance element and the dielectric body are disposed between the first and second conductors. The line is a low impedance line in a frequency f.sub.LC of resonance caused by inductance of the line and capacitance of the resonance unit using an absolute value of a differential negative resistance of the differential negative resistance element as a reference.

An element which oscillates or detects terahertz waves includes a resonance unit including a differential negative resistance element, a first conductor, a second conductor, and a dielectric body, a bias circuit configured to supply a bias voltage to the differential negative resistance element, and a line configured to connect the resonance unit and the bias circuit to each other. The differential negative resistance element and the dielectric body are disposed between the first and second conductors. The line is a low impedance line in a frequency f.sub.LC of resonance caused by inductance of the line and capacitance of the resonance unit using an absolute value of a differential negative resistance of the differential negative resistance element as a reference.

A tunable impedance simulator and impedance multiplier circuit and a system for configuring a second generation voltage-mode conveyor circuit (VCII) as the tunable impedance simulator and impedance multiplier are described. The tunable impedance simulator and impedance multiplier circuit includes one VCII having a positive input terminal connected to a voltage source, a negative input terminal connected to the voltage source, and an impedance terminal Z.sub.0. The impedance terminal Z.sub.0 can be either positive or negative. When the impedance terminal Z.sub.0 is positive, a positive active inductor, a positive capacitance multiplier, and a positive resistance multiplier may be implemented. When the impedance terminal Z.sub.0 is negative, a negative active inductor, a negative capacitance simulator, and a negative resistance simulator may be implemented.

A tunable impedance simulator and impedance multiplier circuit and a system for configuring a second generation voltage-mode conveyor circuit (VCII) as the tunable impedance simulator and impedance multiplier are described. The tunable impedance simulator and impedance multiplier circuit includes one VCII having a positive input terminal connected to a voltage source, a negative input terminal connected to the voltage source, and an impedance terminal Z.sub.0. The impedance terminal Z.sub.0 can be either positive or negative. When the impedance terminal Z.sub.0 is positive, a positive active inductor, a positive capacitance multiplier, and a positive resistance multiplier may be implemented. When the impedance terminal Z.sub.0 is negative, a negative active inductor, a negative capacitance simulator, and a negative resistance simulator may be implemented.

Systems, apparatuses, and methods for implementing a negative resistance circuit for bandwidth extension are disclosed. Within a feedback path of a differential signal path, capacitors are placed on the inputs and outputs of a fully differential amplifier connecting to the differential signal path. In one embodiment, a circuit includes a fully differential amplifier and four capacitors. A first capacitor is coupled between a first signal path and a non-inverting input terminal of the amplifier and a second capacitor is coupled between the first signal path and a non-inverting output terminal of the amplifier. A third capacitor is coupled between a second signal path and an inverting input terminal of the amplifier and a fourth capacitor is coupled between the second signal path and an inverting output terminal of the amplifier. The first and second signal paths carry a differential signal.

A notch filter including an inductor-capacitor tuning circuit is disclosed. The inductor-capacitor tuning circuit may determine a frequency response of the notch filter in accordance with an associated resonant frequency. In some exemplary embodiments, the inductor-capacitor circuit may include a differential inductor divided at a symmetry point and a variable capacitor coupled to the differential inductor at the symmetry point.

A negative impedance circuit including: a first and a second bipolar transistors having a common collector, a base of the first transistor being connected to an emitter of the second transistor; a third and a fourth bipolar transistors having a common collector, a base of the third transistor being connected with an emitter of the fourth transistor; and at least one first impedance formed of one or of a plurality of passive components coupling the common collector of the first and second transistors to the common collector of the third and fourth transistors, a base of the second transistor being coupled to the collector of the third and fourth transistors and a base of the fourth transistor being coupled to the collector of the first and second transistors.

Highly efficient digital domain sub-band based receivers and transmitters.

A negative impedance circuit including: a first and a second bipolar transistors having a common collector, a base of the first transistor being connected to an emitter of the second transistor; a third and a fourth bipolar transistors having a common collector, a base of the third transistor being connected with an emitter of the fourth transistor, and at least one first impedance formed of one or of a plurality of passive components coupling the common collector of the first and second transistors to the common collector of the third and fourth transistors, a base of the second transistor being coupled to the collector of the third and fourth transistors and a base of the fourth transistor being coupled to the collector of the first and second transistors.

A tank circuit includes a tunable resonator subcircuit having an effective parallel resistance that varies with tuning of the tunable resonator subcircuit. The tank circuit further comprises a variable negative-resistance subcircuit coupled in parallel to the tunable resonator subcircuit, where the variable negative-resistance subcircuit is configured to provide a variable negative resistance, so as to increase the effective parallel resistance of the tank circuit. A control circuit is configured to increase the negative resistance presented by the variable negative-resistance subcircuit in response to a change in the tunable resonator subcircuit that lowers the resonant frequency of the tunable resonator subcircuit.