Patent classifications
H03H2017/0081
Downscaler and Method of Downscaling
A hardware downscaling module and downscaling methods for downscaling a two-dimensional array of values. The hardware downscaling unit comprises a first group of one-dimensional downscalers; and a second group of one-dimensional downscalers; wherein the first group of one-dimensional downscalers is arranged to receive a two-dimensional array of values and to perform downscaling in series in a first dimension; and wherein the second group of one-dimensional downscalers is arranged to receive an output from the first group of one-dimensional downscalers and to perform downscaling in series in a second dimension.
METHOD AND DEVICE FOR CONTROLLING FIR FILTER
A method for controlling an FIR filter includes generating, based on operation information, a first and second control data, generating a second amplitude characteristic, and setting filter coefficients of the FIR filter based on the second amplitude characteristic. The first control data indicates an amount of expansion/compression in a frequency axis direction of a first amplitude characteristic that corresponds to a predetermined transfer function that is expressed as a function of an angular frequency, and the amount of expansion/compression is an integer value or a non-integer value. The second control data indicates an amount of shift in the frequency axis direction of the first amplitude characteristic. The second amplitude characteristic is generated by expanding/compressing the first amplitude characteristic in the frequency axis direction in accordance with the first control data and shifting the first amplitude characteristic in the frequency axis direction in accordance with the second control data.
METHOD AND DEVICE FOR CONTROLLING FIR FILTER
A method for controlling an FIR filter includes generating, based on operation information, a first and second control data, generating a second amplitude characteristic, and setting filter coefficients of the FIR filter based on the second amplitude characteristic. The first control data indicates an amount of expansion/compression in a frequency axis direction of a first amplitude characteristic that corresponds to a predetermined transfer function that is expressed as a function of an angular frequency, and the amount of expansion/compression is an integer value or a non-integer value. The second control data indicates an amount of shift in the frequency axis direction of the first amplitude characteristic. The second amplitude characteristic is generated by expanding/compressing the first amplitude characteristic in the frequency axis direction in accordance with the first control data and shifting the first amplitude characteristic in the frequency axis direction in accordance with the second control data.
METHOD AND APPARATUS FOR REDUCED SIZE RF FILTER
A radio frequency (RF) unit and a method for RF isolation. The RF unit includes first and second RF couplers, an RF filter, and an RF canceler connected in parallel with the RF filter. The first RF coupler is configured to receive an input signal. The RF filter is configured to receive a first portion of the input signal from the first RF coupler and attenuate frequencies outside of a passband of the RF filter from the first portion of the input signal. The RF canceler is configured to receive a second portion of the input signal from the first RF coupler and generate a cancellation signal from the second portion of the input signal based on a target frequency band of the RF canceler. The second RF coupler is configured to combine the cancellation signal with an output of the RF filter to generate an output signal.
Optimized multi-pam finite impulse response (FIR) filter
A receiver circuit is disclosed. The receiver circuit includes a multi-PAM input circuit to receive a multi-PAM input symbol. The input symbol exhibits one of multiple threshold levels during a sampling period. The threshold levels correspond to a set of M-bit two's-complement values within a defined set of threshold values. An adaptive filtering circuit includes a first transcoder to transcode the set of M-bit two's-complement values to a set of N-bit values, where N<M. An adaptive filter operates to filter the set of N-bit values to generate a filtered set of data values. A second transcoder transforms the filtered set of data values to a second set of data values that corresponds to a set of filtered M-bit two's-complement values.
METHOD AND SYSTEM FOR ULTRA-NARROWBAND FILTERING WITH SIGNAL PROCESSING USING A CONCEPT CALLED PRISM
Prism signal processing is a new FIR filtering technique that can offer a fully recursive calculation and elegant filter design. Its low design and computational cost may be particularly suited to the autonomous signal processing requirements for the Internet of Things. Arbitrarily narrow band-pass filters may be designed and implemented using a chain of Prisms and a simple yet powerful procedure. Using the described method and system, an ultra-narrowband filter can be evaluated in fractions of a microsecond per sample on a desktop computer. To achieve this update rate using a conventional non-recursive FIR calculation would require supercomputer resources. FPGA embodiments of the system demonstrate computation efficiency and broad applications of the technique.
FRI SPARSE SAMPLING KERNEL FUNCTION CONSTRUCTION METHOD AND CIRCUIT
The invention discloses an FRI sparse sampling kernel function construction method and a circuit. According to the characteristics of an analog input signal and a subsequent parameter estimation algorithm, the method determines the criteria to be satisfied by the sampling kernel, designs a frequency response function of a Fourier series coefficient screening circuit, determines performance parameters of the frequency response function for the sampling kernel, and obtains a sampling kernel function after correction. The circuit is implemented with a Fourier series coefficient screening module and a phase correction module that are connected in cascade. The Fourier series coefficient screening module uses a Chebyshev II low-pass filtering circuit, and the phase correction module uses an all-pass filter circuit. Signals can be directly sparsely sampled according to the rate of innovation of the signals after passing through the sampling kernel circuit, and original characteristic parameters of the signals can be accurately recovered by a parameter estimation algorithm after sparse data is obtained. The FRI sparse sampling kernel provided in the invention is particularly suitable for an FRI sparse sampling system for pulse stream signals, the sampling rate is much lower than a conventional Nyquist sampling rate, and the data acquisition quantity is greatly decreased.
METHOD FOR CARRYING OUT A MORPHING PROCESS
Method for carrying out a morphing process, wherein an output parameter relating to the output of an audio signal outputted into an interior via an audio output device is changed.
Bandwidth configurable signal server
A digital signal processor is designed to channelize an input signal, and includes a channelizer circuit and a plurality of tuning modules. The channelizer circuit is designed to receive an input signal having a first bandwidth and to channelize the input signal into a first set of channels each having a bandwidth smaller than the first bandwidth as a first output signal and to channelize the input signal into a second set of channels having a bandwidth smaller than the first bandwidth as a second output signal. The plurality of tuning modules are designed to receive one or more channels from the first output signal or the second output signal and to further downsample the one or more channels to a user-defined bandwidth at a user-defined center frequency. Each of the plurality of tuning modules include a plurality of FIR filter blocks and a memory having a plurality of FIR filter coefficients.
Method for equivalent high sampling rate FIR filtering based on FPGA
The present invention provides a method for equivalent high sampling rate FIR filtering based on FPGA, first, the coefficients h(k) of FIR filter are found by using MATLAB, multiplied by an integer and then rounded for the purpose that the rounded coefficients h(k) can be directly used into a FPGA, then the ADC's output of high data rate fs is lowered by dividing the ADC's output x(n) into M parallel data streams xi(n) of low data rate, and the M×L samples in one clock cycle is obtained by delaying the M parallel data streams xi(n) simultaneously by 1, 2, . . . , L′ periods of the synchronous clock, at last, the samples yi(n) of FIR filtering output is calculated according to the samples selected from the M×L samples, and the filtered data y(n) of data rate fs is obtained by putting the samples yi(n) together in ascending order of i. Thus, the continuous FIR filtering of an ADC's output sampled with high sampling rate is realized, while the data rates before and after the FIR filtering are unchanged.