A method and an apparatus for signal processing: implementing step-by-step orthogonal decomposition of an original signal to be inputted; on the basis of the number of layers of orthogonal decomposition and the edge high frequency bandwidth of the original signal after orthogonal decomposition, generating a finite-length unit impulse response FIR filter; using the FIR filter to filter the edge high-frequency signal of the original signal; and, after passing the signal obtained after filtering and the low frequency signal obtained at each stage of orthogonal decomposition through an orthogonal filter bank, implementing signal synthesis processing.

A noise generator for generating a noise signal over a frequency spectrum has a first noise source and a first digital filter for a first frequency band, a second noise source and a second digital filter for a second frequency band, and an interpolator and a combiner. The first digital filter has a first sample rate and the second digital filter has a second sample rate, wherein the ratio between the second sample rate and the first sample rate, with regard to a sign, corresponds to a ratio between center frequencies of the second frequency band and the first frequency band, wherein an edge of the second digital filters which determines a lower frequency band limit is steeper than an edge of the first digital filter which determines an upper frequency band limit. The interpolator is configured to adjust an output signal of the first digital filter, with regard to its sample rate, to a sample rate of the second digital filter, wherein the combiner is configured to combine the adjusted output signal from the interpolator and the output signal of the second digital filter.

The present invention discloses a method for determining FIR digital filter coefficients providing a compensated amplitude response of a conventional windowing filter. The compensation allows independent control of passband and stopband specifications, while narrowing the transition bandwidths. The method comprises the steps of summing an auxiliary impulse response to a windowing impulse response, wherein the auxiliary impulse response has a phase response identical to that of the windowing impulse response, and an amplitude response comprising frequency shifted pulses positioned to induce the required compensation. The summing is followed by a modulation with a discrete time function to obtain the filter impulse response. The invention discloses a characterization of the pulse compensation on the amplitude response, a filter design method and computer program based on this characterization. The invention discloses an FIR filter device with coefficients set by this method.

There are provided a signal generator capable of flexibly increasing the number of taps while realizing high-speed emphasis switching and an emphasis switching method using the signal generator. A signal generator includes: an emphasis addition circuit including at least one finite impulse response (FIR) filter unit that generates an emphasis waveform pattern by adding an emphasis to a pattern of a pulse amplitude modulation (PAM) signal including multi-values which are two or more values; and a tap value setting unit that switches M tap values C(0), C(?1), . . . , and C(1?M) and sets the M tap values C(0), C(?1), . . . , and C(1?M) to each FIR filter unit according to an emphasis switching request from a DUT 100. The FIR filter unit is configured on an FPGA or an ASIC.

A DLL includes a delay line with two phase outputs, a gater coupled with the delay line phase outputs, a PFD coupled with gater outputs, a PD coupled with PFD outputs, a retimer coupled with PD outputs, and a loop filter with inputs coupled with the retimer and a speed control output coupled with the delay line. The gater passes signals on its two inputs to its two outputs, apart from a first pulse on its first input. The PD determines if the second gated signal leads or lags the first gated signal. The retimer retimes PD output signals to be aligned with a delay line input signal. The loop filter uses the retimed PD output signals to determine if the delay line should delay more or delay less, and outputs a speed control signal to control the delay line speed.

Methods, devices, and systems are provided for improving efficiency of power quality and revenue-based computations which include receiving an input signal and oversampling the input signal to generate an oversampled data stream. In a first signal path, the oversampled data stream is filtered to generate a filtered data stream, and the filtered data stream is decimated to generate a decimated data stream. The filtered data stream and the decimated data stream include waveform data capable of use for generating power quality analysis information. In a second signal path, the oversampled data stream is downsampled to generate a downsampled data stream, and revenue quality power consumption data is generated based at least in part upon meta data from the downsampled data stream. Power quality data is generated based at least in part upon the decimated data stream and associated meta data.

A filter device includes: delay units serially connected to delay an input signal and output a delayed signal; multiplication units multiplying the delayed signal by a filter coefficient based on a predetermined value and a multiplying factor adjustment value; a coefficient adjustment unit that, when a multiplication result obtained by multiplying the predetermined value by the multiplying factor adjustment value exceeds a maximum value of a filter-coefficient representation range, divides the multiplication result exceeding the maximum value by the maximum value, and outputs a quotient of division as a coefficient adjustment value; a signal conversion unit outputting a signal obtained by adding after-filter-coefficient-multiplication signals outputted by the multiplication units and an adjusted signal obtained by adjusting a corresponding delayed signal using the coefficient adjustment value; and a division unit generating an output signal by dividing the signal outputted by the signal conversion unit by the multiplying factor adjustment value.

A radio frequency (RF) unit and a method for RF isolation. The RF unit includes first and second RF couplers, an RF filter, and an RF canceler connected in parallel with the RF filter. The first RF coupler is configured to receive an input signal. The RF filter is configured to receive a first portion of the input signal from the first RF coupler and attenuate frequencies outside of a passband of the RF filter from the first portion of the input signal. The RF canceler is configured to receive a second portion of the input signal from the first RF coupler and generate a cancellation signal from the second portion of the input signal based on a target frequency band of the RF canceler. The second RF coupler is configured to combine the cancellation signal with an output of the RF filter to generate an output signal.

A circuit includes a transmitter, a transmission line, and a receiver coupled to the transmitter through the transmission line, the transmission line used to transmit data at high-speed rates. At least one of the transmitter or receiver has associated therewith an unmatched termination, wherein either the transmitter or the receiver includes a finite impulse response (FIR) filter configured to cancel a reflected signal at a cancellation point situated at an input of the receiver, at an input of a driver, or at an output of the driver, the driver being coupled to an output of the transmitter, such that the reflected signal is substantially removed from the signal detected by the receiver.

A Finite Impulse Response (FIR) filter that reduces the complexity of the hardware required for a filter with a high decimation factor while achieving similar performance of prior art poly-phase filters of greater complexity. The FIR filter includes a small number of multiply-and-accumulate (MAC) units connected in parallel to each other between an input stream and an output stream. The MAC units are provided with coefficients from a memory. In an example implementation, the memory is addressed by a counter and the output of the memory selected by a multiplexer for suppling the coefficients.