A finite impulse response (FIR) filter includes a plurality of registers. The data input terminal of each register is directly coupled to the input of the FIR filter. A new data value is passed to each register on each clock cycle of a filter clock signal. Only one of the registers processes the data value on each clock cycle. A ring counter is coupled to the registers and determines which register processes the data value on each dock cycle.

Various exemplary embodiments are directed to methods including obtaining an input sample magnitude, filtering the obtained input sample magnitude, generating a sample-to-sample difference based on the filtered input sample magnitude, and engaging an actuator in accordance with a determination that the sample-to-sample difference satisfies a rate threshold. In addition, various exemplary embodiments are directed to devices including a processor, a control sensor operatively coupled to the processor and operable to obtain an input sample magnitude, an input filter operatively coupled to the processor and operable to filter the at least one obtained input magnitude sample, a non-transitory computer-readable medium operatively coupled to the processor and including a rate engine operable to generate a sample-to-sample difference based on the filtered input sample magnitude, and to generate a determination that the sample-to-sample difference satisfies a rate threshold, and a control actuator operatively coupled to the processor and operable to engage an operation mechanism in accordance with the determination that the sample-to-sample difference satisfies a rate threshold.

A method is provided that includes performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers, wherein determination of values of implied bits of leading bit encoded mantissas of the floating point numbers is performed in parallel with multiplication of the encoded mantissas, and storing, by the processor, a result of the floating point multiply instruction in a storage location indicated by the floating point multiply instruction.

A method is provided that includes performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers, wherein determination of values of implied bits of leading bit encoded mantissas of the floating point numbers is performed in parallel with multiplication of the encoded mantissas, and storing, by the processor, a result of the floating point multiply instruction in a storage location indicated by the floating point multiply instruction.

A digital filter according to the disclosure includes a processing circuit having a memory and a number of parallel processing circuits. The parallel processing circuits perform a convolution operations based on input data and function data that is accessed from the memory. The filter further includes a serializer for serializing data that is received from the processing circuits. A clock generator circuit provides a first clock signal to the processing circuit and a second clock signal to the serializer. The frequency of the second clock signal is greater than that of the first clock signal.

A digital filter according to the disclosure includes a processing circuit having a memory and a number of parallel processing circuits. The parallel processing circuits perform a convolution operations based on input data and function data that is accessed from the memory. The filter further includes a serializer for serializing data that is received from the processing circuits. A clock generator circuit provides a first clock signal to the processing circuit and a second clock signal to the serializer. The frequency of the second clock signal is greater than that of the first clock signal.

A system for driving a transducer having a plurality of coils, the system comprising: a modulator for outputting a digital output signal representative of a received analogue input signal at a modulator output; a clock controlled delay element for applying a delay to the digital output signal to generate a first delayed signal at a delay element output; wherein the modulator output is couplable to a first coil of the plurality of the coils of the transducer and the delay element output is couplable to a second coil of the plurality of coils of the transducer.

A system for driving a transducer having a plurality of coils, the system comprising: a modulator for outputting a digital output signal representative of a received analogue input signal at a modulator output; a clock controlled delay element for applying a delay to the digital output signal to generate a first delayed signal at a delay element output; wherein the modulator output is couplable to a first coil of the plurality of the coils of the transducer and the delay element output is couplable to a second coil of the plurality of coils of the transducer.

An oversampling filter oversamples a digital audio signal. A ΔΣ modulator delta-sigma modulates a signal output from the oversampling filter. A D/A converter converts a signal output from the ΔΣ modulator into an analog audio signal. The oversampling filter includes a processor configured to run firmware and a computational algorithm is configurable based on the firmware.

An oversampling filter oversamples a digital audio signal. A ΔΣ modulator delta-sigma modulates a signal output from the oversampling filter. A D/A converter converts a signal output from the ΔΣ modulator into an analog audio signal. The oversampling filter includes a processor configured to run firmware and a computational algorithm is configurable based on the firmware.