A system comprises a digital processing circuit, a frequency modulator, an amplitude modulator, and an adder. The digital processing circuit receives an input signal and a correlation signal and generates a frequency tuning parameter and an amplitude modulation parameter. The frequency modulator generates a frequency modulation signal and the correlation signal. The amplitude modulator receives the amplitude modulation parameter and generates an amplitude modulation signal. The adder receives the frequency tuning parameter and the frequency modulation signal and generates a control signal. In some implementations, the system further comprises a DC feedback circuit that receives the input signal and generates a DC compensation signal. In some implementations, the system further comprises a temperature sensor, a temperature compensation circuit, and a second adder.

A system comprises a digital processing circuit, a frequency modulator, an amplitude modulator, and an adder. The digital processing circuit receives an input signal and a correlation signal and generates a frequency tuning parameter and an amplitude modulation parameter. The frequency modulator generates a frequency modulation signal and the correlation signal. The amplitude modulator receives the amplitude modulation parameter and generates an amplitude modulation signal. The adder receives the frequency tuning parameter and the frequency modulation signal and generates a control signal. In some implementations, the system further comprises a DC feedback circuit that receives the input signal and generates a DC compensation signal. In some implementations, the system further comprises a temperature sensor, a temperature compensation circuit, and a second adder.

An electric machine with variable torque generation having a tunable Halbach array configuration. The electric machine includes a magnet assembly for generating a magnetic field. The magnet assembly includes a plurality of fixed magnets disposed in a ring arrangement so that fixed magnets having a north pole faced toward the rotor or stator are alternated with fixed magnets having a south pole faced toward the rotor or stator, a plurality of rotatable magnets disposed within a respective slot formed between two adjacent fixed magnets, a drive assembly for turning the rotatable magnets within the slots to vary the magnetic field generated by the magnet assembly in the rotor or stator, the drive assembly configured to turn the rotatable magnets between a first position wherein the magnetic field in the rotor or stator is augmented and a second position wherein the magnetic field in the rotor or stator is cancelled.

An electric machine with variable torque generation having a tunable Halbach array configuration. The electric machine includes a magnet assembly for generating a magnetic field. The magnet assembly includes a plurality of fixed magnets disposed in a ring arrangement so that fixed magnets having a north pole faced toward the rotor or stator are alternated with fixed magnets having a south pole faced toward the rotor or stator, a plurality of rotatable magnets disposed within a respective slot formed between two adjacent fixed magnets, a drive assembly for turning the rotatable magnets within the slots to vary the magnetic field generated by the magnet assembly in the rotor or stator, the drive assembly configured to turn the rotatable magnets between a first position wherein the magnetic field in the rotor or stator is augmented and a second position wherein the magnetic field in the rotor or stator is cancelled.

In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.

In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.

This application discloses a chip and a signal level shifter circuit for use on a mobile terminal such as a charger or an adapter. The chip is co-packaged with a first silicon-based driver die and a second silicon-based driver die that are manufactured by using a BCD technology, and a first gallium nitride die and a second gallium nitride die that are manufactured by using a gallium nitride technology. A first silicon-based circuit is integrated on the first silicon-based driver die, a second silicon-based circuit is integrated on the second silicon-based driver die, and a high-voltage resistant gallium nitride circuit is integrated on the first gallium nitride die. In this way, it can be ensured that a second low-voltage silicon-based driver die manufactured by using a low-voltage BCD technology is not damaged by a high input voltage, thereby reducing costs of the chip.

This application discloses a chip and a signal level shifter circuit for use on a mobile terminal such as a charger or an adapter. The chip is co-packaged with a first silicon-based driver die and a second silicon-based driver die that are manufactured by using a BCD technology, and a first gallium nitride die and a second gallium nitride die that are manufactured by using a gallium nitride technology. A first silicon-based circuit is integrated on the first silicon-based driver die, a second silicon-based circuit is integrated on the second silicon-based driver die, and a high-voltage resistant gallium nitride circuit is integrated on the first gallium nitride die. In this way, it can be ensured that a second low-voltage silicon-based driver die manufactured by using a low-voltage BCD technology is not damaged by a high input voltage, thereby reducing costs of the chip.

Various embodiments of the present application are directed towards a level shifter with temperature compensation. In some embodiments, the level shifter comprises a transistor, a first resistor, and a second resistor. The first resistor is electrically coupled from a first source/drain of the transistor to a supply node, and the second resistor is electrically coupled from a second source/drain of the transistor to a reference node. Further, the first and second resistors have substantially the same temperature coefficients and comprise group III-V semiconductor material. By having both the first and second resistors, the output voltage of the level shifter is defined by the resistance ratio of the resistors. Further, since the first and second resistors have the same temperature coefficients, temperature induced changes in resistance is largely cancelled out in the ratio and the output voltage is less susceptible to temperature induced change than the first and second resistors individually.

Various embodiments of the present application are directed towards a level shifter with temperature compensation. In some embodiments, the level shifter comprises a transistor, a first resistor, and a second resistor. The first resistor is electrically coupled from a first source/drain of the transistor to a supply node, and the second resistor is electrically coupled from a second source/drain of the transistor to a reference node. Further, the first and second resistors have substantially the same temperature coefficients and comprise group III-V semiconductor material. By having both the first and second resistors, the output voltage of the level shifter is defined by the resistance ratio of the resistors. Further, since the first and second resistors have the same temperature coefficients, temperature induced changes in resistance is largely cancelled out in the ratio and the output voltage is less susceptible to temperature induced change than the first and second resistors individually.