A chip with pad tracking having an input/output buffer (I/O buffer), a pad, and a bias circuit. The I/O buffer is powered by a first power and is coupled to the pad. The pad is coupled to the system power. The bias circuit generates a bias signal to be transferred to the I/O buffer to block a leakage path within the I/O buffer when the system power is on and the first power is off. The bias circuit is a voltage divider which generates a divided voltage as the bias signal. In an example, the bias circuit is powered by a second power that is independent from the first power and is not drawn from the pad. In another example, a power terminal of the bias circuit is coupled to an electrostatic discharging bus, and the pad is coupled to the electrostatic discharging bus through a diode.

A chip with pad tracking having an input/output buffer (I/O buffer), a pad, and a bias circuit. The I/O buffer is powered by a first power and is coupled to the pad. The pad is coupled to the system power. The bias circuit generates a bias signal to be transferred to the I/O buffer to block a leakage path within the I/O buffer when the system power is on and the first power is off. The bias circuit is a voltage divider which generates a divided voltage as the bias signal. In an example, the bias circuit is powered by a second power that is independent from the first power and is not drawn from the pad. In another example, a power terminal of the bias circuit is coupled to an electrostatic discharging bus, and the pad is coupled to the electrostatic discharging bus through a diode.

A high-voltage tolerant circuit includes a first level shifter responsive to an input signal having a first logic high voltage and a first logic low voltage for providing a first intermediate signal having the first logic high voltage and a second logic low voltage referenced to a second reference voltage higher than the first logic low voltage, a second level shifter responsive to the input signal for providing a second intermediate signal having a second logic high voltage referenced to a first reference voltage lower than the first logic high voltage, and the first logic low voltage, an output stage responsive to the first and second intermediate signals for providing an output signal having the first logic high voltage and the first logic low voltage, and a reference voltage generation circuit providing the second logic high and second logic low voltages without drawing current from the reference voltage generation circuit.

A high-voltage tolerant circuit includes a first level shifter responsive to an input signal having a first logic high voltage and a first logic low voltage for providing a first intermediate signal having the first logic high voltage and a second logic low voltage referenced to a second reference voltage higher than the first logic low voltage, a second level shifter responsive to the input signal for providing a second intermediate signal having a second logic high voltage referenced to a first reference voltage lower than the first logic high voltage, and the first logic low voltage, an output stage responsive to the first and second intermediate signals for providing an output signal having the first logic high voltage and the first logic low voltage, and a reference voltage generation circuit providing the second logic high and second logic low voltages without drawing current from the reference voltage generation circuit.

The present disclosure relates to contactor, and device and method for controlling same. A control device for a contactor comprises a high side control unit, a first low side control unit, a second low side control unit, a freewheeling unit, and a controller. The high side control unit is configured to switch on or switch off the connection of the first magnetic unit and the second magnetic unit of the contactor with a power supply. The first low side control unit is configured to switch on or switch off the connection of the first magnetic unit with the reference voltage node. The second low side control unit is configured to switch on or switch off the connection of the second magnetic unit with the reference voltage node. The freewheeling unit is connected across a branch comprising a first magnetic unit and a first low side control unit and connected across a branch comprising a second magnetic unit and a second low side control unit. The controller is configured to control the operation of the high side control unit, the first low side control unit, and the second low side control unit. Embodiments of the present disclosure may enable intelligent control of contactors with simple control logic.

The present disclosure relates to contactor, and device and method for controlling same. A control device for a contactor comprises a high side control unit, a first low side control unit, a second low side control unit, a freewheeling unit, and a controller. The high side control unit is configured to switch on or switch off the connection of the first magnetic unit and the second magnetic unit of the contactor with a power supply. The first low side control unit is configured to switch on or switch off the connection of the first magnetic unit with the reference voltage node. The second low side control unit is configured to switch on or switch off the connection of the second magnetic unit with the reference voltage node. The freewheeling unit is connected across a branch comprising a first magnetic unit and a first low side control unit and connected across a branch comprising a second magnetic unit and a second low side control unit. The controller is configured to control the operation of the high side control unit, the first low side control unit, and the second low side control unit. Embodiments of the present disclosure may enable intelligent control of contactors with simple control logic.

According to one embodiment, a drive device includes a drive circuit configured to drive a semiconductor device. The semiconductor device includes first to fourth electrodes, a semiconductor member, and an insulating member. The semiconductor member includes first to fourth semiconductor region. The first semiconductor region includes first to third partial regions. The first semiconductor region is between the first electrode and the second semiconductor region. The third semiconductor region is between the first and second semiconductor regions. The fourth semiconductor region is between the first electrode and the first semiconductor region. The second electrode is electrically connected to the second semiconductor region. The first partial region is between the fourth semiconductor region and the third electrode. The second partial region is between the fourth semiconductor region and the fourth electrode. A part of the insulating member is provided between the semiconductor member and the third and fourth electrodes.

According to one embodiment, a drive device includes a drive circuit configured to drive a semiconductor device. The semiconductor device includes first to fourth electrodes, a semiconductor member, and an insulating member. The semiconductor member includes first to fourth semiconductor region. The first semiconductor region includes first to third partial regions. The first semiconductor region is between the first electrode and the second semiconductor region. The third semiconductor region is between the first and second semiconductor regions. The fourth semiconductor region is between the first electrode and the first semiconductor region. The second electrode is electrically connected to the second semiconductor region. The first partial region is between the fourth semiconductor region and the third electrode. The second partial region is between the fourth semiconductor region and the fourth electrode. A part of the insulating member is provided between the semiconductor member and the third and fourth electrodes.

A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.