A switching component and switch assembly. The switching component comprises a first control node, a common node, a plurality of intermediate nodes, a second control node, and a capacitive node; a plurality of transistors connected in series between the control node and the common node, one of the plurality of intermediate nodes being defined between each series connected pair of transistors, each transistor of the plurality of transistors having a gate coupled to the second control node; and a plurality of capacitive components, one capacitive component being coupled between each intermediate node and the capacitive node, a voltage at the capacitive node being configured to be varied with a voltage at the second control node such that, at each intermediate node, the capacitive component is configured to accrue an opposite charge to the transistors.

A method of generating multiple gating signals for a multi-gated input/output (I/O) system. The system includes an output level shifter and an output driver which are coupled in series between an output node of a core circuit and an external terminal of a corresponding system. The method includes: generating first and second gating signals having corresponding first and second waveforms, the first waveform transitioning from a non-enabling state to an enabling state before the second waveform transitions from the non-enabling state to the enabling state; receiving the first gating signal at the output level shifter; and receiving the second gating signal at the output driver.

A power-on reset circuit 10 has: an enhancement-type PMOS transistor P1 whose source is connected to VDD and whose drain is connected to node VJG; a depletion-type NMOS transistor D1 whose drain is connected to the node VJG; a first resistor portion having resistors R1, R2 that are connected in series, and whose one end is connected to a source of the depletion-type NMOS transistor D1, and whose another end is connected to GND, and at which a region between the resistors R1, R2 is connected to a gate of the enhancement-type PMOS transistor P1; and an inverter whose input is connected to the node VJG, and that outputs a reset signal.

A power-on reset circuit 10 has: an enhancement-type PMOS transistor P1 whose source is connected to VDD and whose drain is connected to node VJG; a depletion-type NMOS transistor D1 whose drain is connected to the node VJG; a first resistor portion having resistors R1, R2 that are connected in series, and whose one end is connected to a source of the depletion-type NMOS transistor D1, and whose another end is connected to GND, and at which a region between the resistors R1, R2 is connected to a gate of the enhancement-type PMOS transistor P1; and an inverter whose input is connected to the node VJG, and that outputs a reset signal.

A circuit is disclosed. The circuit includes a first transistor including a first drain terminal, a first gate terminal and a first source terminal, a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal, and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation. In one aspect, the first transistor includes gallium nitride (GaN). In another aspect, the circuit further includes a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.

A circuit is disclosed. The circuit includes a first transistor including a first drain terminal, a first gate terminal and a first source terminal, a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal, and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation. In one aspect, the first transistor includes gallium nitride (GaN). In another aspect, the circuit further includes a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.

An integrated circuit, including: a first current source; a second current source provided in parallel to the first current source; a first resistor with one end coupled to an output of the first current source; a first bipolar transistor that is diode-connected and is coupled to the other end of the first resistor; a second bipolar transistor that is diode-connected and is coupled to an output of the second current source; a second resistor coupled to the second bipolar transistor; and an output circuit configured to output a voltage based on a first voltage outputted from the first current source and a second voltage outputted from the second current source.

An integrated circuit, including: a first current source; a second current source provided in parallel to the first current source; a first resistor with one end coupled to an output of the first current source; a first bipolar transistor that is diode-connected and is coupled to the other end of the first resistor; a second bipolar transistor that is diode-connected and is coupled to an output of the second current source; a second resistor coupled to the second bipolar transistor; and an output circuit configured to output a voltage based on a first voltage outputted from the first current source and a second voltage outputted from the second current source.

Circuits and methods that control a rate of change of a drain voltage as a function of time in a transistor are disclosed. In one aspect, the circuit includes a transistor having a gate terminal that controls operation of the transistor, and a control circuit coupled to the gate terminal and arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and further arranged to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, where the first rate is different than the second rate.

Circuits and methods that control a rate of change of a drain voltage as a function of time in a transistor are disclosed. In one aspect, the circuit includes a transistor having a gate terminal that controls operation of the transistor, and a control circuit coupled to the gate terminal and arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and further arranged to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, where the first rate is different than the second rate.