Patent classifications
H03K3/014
Apparatus and method for shortening start-up time of a crystal oscillator
A fast start-up oscillator circuit to reduce a start-up time of a crystal oscillator is presented. The circuit contains a crystal resonator to output a first oscillation signal and a tunable RC oscillator to output a second oscillation signal. A driver is coupled between the tunable RC oscillator and the crystal resonator The driver transfers the second oscillation signal output from the tunable RC oscillator to the crystal resonator. The driver drives the crystal resonator, and a feedback circuit connected between the crystal resonator and the tunable RC oscillator to align a phase of the tunable RC oscillator with a phase of the crystal resonator based on the oscillation signal output by the crystal resonator.
Apparatus and method for shortening start-up time of a crystal oscillator
A fast start-up oscillator circuit to reduce a start-up time of a crystal oscillator is presented. The circuit contains a crystal resonator to output a first oscillation signal and a tunable RC oscillator to output a second oscillation signal. A driver is coupled between the tunable RC oscillator and the crystal resonator The driver transfers the second oscillation signal output from the tunable RC oscillator to the crystal resonator. The driver drives the crystal resonator, and a feedback circuit connected between the crystal resonator and the tunable RC oscillator to align a phase of the tunable RC oscillator with a phase of the crystal resonator based on the oscillation signal output by the crystal resonator.
Oscillator, method of operating the same, and PWM controller including the same
An oscillator for a pulse width modulation (PWM) controller includes an oscillation circuit including a capacitor and configured to generate a first pulse signal by charging and discharging the capacitor, a frequency divider configured to generate a second pulse signal based on the first pulse signal, the second pulse signal having a lower frequency than the first pulse signal, and an oscillation control circuit coupled to the oscillation circuit and the frequency divider and configured to generate control signals for holding the charging and discharging of the capacitor during an oscillation holding operation.
Oscillator, method of operating the same, and PWM controller including the same
An oscillator for a pulse width modulation (PWM) controller includes an oscillation circuit including a capacitor and configured to generate a first pulse signal by charging and discharging the capacitor, a frequency divider configured to generate a second pulse signal based on the first pulse signal, the second pulse signal having a lower frequency than the first pulse signal, and an oscillation control circuit coupled to the oscillation circuit and the frequency divider and configured to generate control signals for holding the charging and discharging of the capacitor during an oscillation holding operation.
METHOD AND SYSTEM FOR ARBITRARY OPTICAL PULSE GENERATION
A system, method, and apparatus for continuous seed laser pulses supplied to a CW pumped pre-amplifier and/or power-amplifier chain comprises an optical modulator configured to impress pulse signals on an optical signal, a waveform generator configured to establish a structure of the optical signal, and a keep-alive circuit that generates a continuous electrical pulse pattern provided to the optical modulator, wherein the system provides a continuous seed laser pulse structure.
METHOD AND SYSTEM FOR ARBITRARY OPTICAL PULSE GENERATION
A system, method, and apparatus for continuous seed laser pulses supplied to a CW pumped pre-amplifier and/or power-amplifier chain comprises an optical modulator configured to impress pulse signals on an optical signal, a waveform generator configured to establish a structure of the optical signal, and a keep-alive circuit that generates a continuous electrical pulse pattern provided to the optical modulator, wherein the system provides a continuous seed laser pulse structure.
Low power electronic oscillators
An oscillator arrangement is provided, comprising a relaxation oscillator having an active state and an inactive state; a bias current circuit portion arranged to provide a bias current to the relaxation oscillator during said active state; and an electronic switch arranged to isolate said relaxation oscillator from the bias current circuit portion when in said inactive state. The oscillator arrangement is arranged to store an internal voltage value associated with said bias current and the bias current circuit portion is arranged to use the stored internal voltage value to generate the bias current when the oscillator is started up from the inactive state to the active state.
Low power electronic oscillators
An oscillator arrangement is provided, comprising a relaxation oscillator having an active state and an inactive state; a bias current circuit portion arranged to provide a bias current to the relaxation oscillator during said active state; and an electronic switch arranged to isolate said relaxation oscillator from the bias current circuit portion when in said inactive state. The oscillator arrangement is arranged to store an internal voltage value associated with said bias current and the bias current circuit portion is arranged to use the stored internal voltage value to generate the bias current when the oscillator is started up from the inactive state to the active state.
SYSTEMS AND TECHNIQUES FOR TIMING MISMATCH REDUCTION
Systems and techniques to offset conditions affecting propagation delay of a clock signal in a memory device. These include a device that includes a clock adjustment circuit, comprising a differential amplifier, an inverter coupled to a first output of the differential amplifier, and a swing oscillator driver coupled to a second output of the inverter and an input of the differential amplifier. The swing oscillator driver includes a series of transistors, a signal path coupled to at least a first transistor of the series of transistors, wherein the signal path when in operation transmits a signal having a first voltage, and a strength control circuit coupled to the signal path, wherein the strength control circuit when in operation adjusts the first voltage of the signal to a second voltage.
SYSTEMS AND TECHNIQUES FOR TIMING MISMATCH REDUCTION
Systems and techniques to offset conditions affecting propagation delay of a clock signal in a memory device. These include a device that includes a clock adjustment circuit, comprising a differential amplifier, an inverter coupled to a first output of the differential amplifier, and a swing oscillator driver coupled to a second output of the inverter and an input of the differential amplifier. The swing oscillator driver includes a series of transistors, a signal path coupled to at least a first transistor of the series of transistors, wherein the signal path when in operation transmits a signal having a first voltage, and a strength control circuit coupled to the signal path, wherein the strength control circuit when in operation adjusts the first voltage of the signal to a second voltage.