A system for providing security in a computer system is provided. The system includes a ring oscillator including a plurality of logic gates connected in a ring configuration. The system also includes logic circuits to start the ring oscillator by a ring-enable signal and a clock signal provided to a clock input of at least one controlled logic gate of the plurality of logic gates. The clock signal controls the at least one controlled logic gate and thereby synchronizes the ring oscillator to the clock signal. The clock signal is provided to the clock input for a predetermined warm-up duration, and thereafter, the logic circuits restart and operate the ring oscillator without the clock signal.

A system for providing security in a computer system is provided. The system includes a ring oscillator including a plurality of logic gates connected in a ring configuration. The system also includes logic circuits to start the ring oscillator by a ring-enable signal and a clock signal provided to a clock input of at least one controlled logic gate of the plurality of logic gates. The clock signal controls the at least one controlled logic gate and thereby synchronizes the ring oscillator to the clock signal. The clock signal is provided to the clock input for a predetermined warm-up duration, and thereafter, the logic circuits restart and operate the ring oscillator without the clock signal.

In a semiconductor integrated circuit, a first analog circuit block operates by a voltage applied between a first node and a third node. Each of a plurality of first current sources has a first end connected to the third node and a second end connected to the first analog circuit block. The plurality of first current sources function as current sourcing or current sinking for the first analog circuit block. A first switch group is provided between the plurality of first current sources and the first analog circuit block, and in a test mode, individually switches electrical connection of the second end of each of the plurality of first current sources from the first analog circuit block to a second node.

In a semiconductor integrated circuit, a first analog circuit block operates by a voltage applied between a first node and a third node. Each of a plurality of first current sources has a first end connected to the third node and a second end connected to the first analog circuit block. The plurality of first current sources function as current sourcing or current sinking for the first analog circuit block. A first switch group is provided between the plurality of first current sources and the first analog circuit block, and in a test mode, individually switches electrical connection of the second end of each of the plurality of first current sources from the first analog circuit block to a second node.

A start-up circuit for a ring current-controlled oscillator (CCO) includes a replica CCO current generator, a replica ring CCO, and a buffer. The ring CCO is connected to a CCO driver and the buffer. The CCO driver generates a CCO current based on a reference current. The ring CCO generates a CCO output voltage at a first oscillating frequency based on the CCO current. The replica CCO current generator generates a replica CCO current based on a reference voltage. The replica ring CCO generates a replica CCO output voltage at a second oscillating frequency based on the replica CCO current. The buffer provides a first current to the ring CCO when the first oscillating frequency is lower than a desired oscillating frequency, and drains a second current from the ring CCO when the first oscillating frequency is greater than the desired oscillating frequency.

Systems and techniques to offset conditions affecting propagation delay of a clock signal in a memory device. These include a device that includes a clock adjustment circuit, comprising a differential amplifier, an inverter coupled to a first output of the differential amplifier, and a swing oscillator driver coupled to a second output of the inverter and an input of the differential amplifier. The swing oscillator driver includes a series of transistors, a signal path coupled to at least a first transistor of the series of transistors, wherein the signal path when in operation transmits a signal having a first voltage, and a strength control circuit coupled to the signal path, wherein the strength control circuit when in operation adjusts the first voltage of the signal to a second voltage.

Systems and techniques to offset conditions affecting propagation delay of a clock signal in a memory device. These include a device that includes a clock adjustment circuit, comprising a differential amplifier, an inverter coupled to a first output of the differential amplifier, and a swing oscillator driver coupled to a second output of the inverter and an input of the differential amplifier. The swing oscillator driver includes a series of transistors, a signal path coupled to at least a first transistor of the series of transistors, wherein the signal path when in operation transmits a signal having a first voltage, and a strength control circuit coupled to the signal path, wherein the strength control circuit when in operation adjusts the first voltage of the signal to a second voltage.

An oscillator for a pulse width modulation (PWM) controller includes an oscillation circuit including a capacitor and configured to generate a first pulse signal by charging and discharging the capacitor, a frequency divider configured to generate a second pulse signal based on the first pulse signal, the second pulse signal having a lower frequency than the first pulse signal, and an oscillation control circuit coupled to the oscillation circuit and the frequency divider and configured to generate control signals for holding the charging and discharging of the capacitor during an oscillation holding operation.

An oscillator for a pulse width modulation (PWM) controller includes an oscillation circuit including a capacitor and configured to generate a first pulse signal by charging and discharging the capacitor, a frequency divider configured to generate a second pulse signal based on the first pulse signal, the second pulse signal having a lower frequency than the first pulse signal, and an oscillation control circuit coupled to the oscillation circuit and the frequency divider and configured to generate control signals for holding the charging and discharging of the capacitor during an oscillation holding operation.

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks on-the-fly, e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.