A pulse-based flip flop circuit includes; a pulse generator generating a pulse signal and an inverted pulse signal, a scan hold buffer holding a scan input signal for a delay time, and a latch circuit including an intermediate node receiving one of a data signal and the scan input signal in response to a scan enable signal, the pulse signal and the inverted pulse signal. The pulse generator circuit includes; a direct path providing a clock signal as a direct path input to a NAND circuit, a delay path including a number of stages configured to delay the clock signal and provide a delayed clock signal as a delay path input to NAND circuit, wherein the NAND circuit performs a NAND operation on the direct path input and the delay path input to generate the inverted pulse signal, and a feedback path providing the pulse signal to a first stage among the number of stages of the delay path.

A pulse-based flip flop circuit includes; a pulse generator generating a pulse signal and an inverted pulse signal, a scan hold buffer holding a scan input signal for a delay time, and a latch circuit including an intermediate node receiving one of a data signal and the scan input signal in response to a scan enable signal, the pulse signal and the inverted pulse signal. The pulse generator circuit includes; a direct path providing a clock signal as a direct path input to a NAND circuit, a delay path including a number of stages configured to delay the clock signal and provide a delayed clock signal as a delay path input to NAND circuit, wherein the NAND circuit performs a NAND operation on the direct path input and the delay path input to generate the inverted pulse signal, and a feedback path providing the pulse signal to a first stage among the number of stages of the delay path.

A transmitter circuit that receives parallel signals and outputs a serial signal in response to the parallel signals may include; a clock generator generating first clock signals having different respective phases, a multiplexer including selection circuits respectively configured to selectively provide at least two of the parallel signals to an output node in response to at least two of the first clock signals, and an output driver generating the serial signal by amplifying a signal at the output node.

A transmitter circuit that receives parallel signals and outputs a serial signal in response to the parallel signals may include; a clock generator generating first clock signals having different respective phases, a multiplexer including selection circuits respectively configured to selectively provide at least two of the parallel signals to an output node in response to at least two of the first clock signals, and an output driver generating the serial signal by amplifying a signal at the output node.

The present disclosure provides a PWM circuit, a modulation method, and an electronic device, and relates to the field of communication technologies. In the PWM circuit, a control word providing circuit can generate, based on an obtained target duty cycle, two target frequency control words with a ratio of the target duty cycle, and output the two target frequency control words to a pulse generation circuit; and the pulse generation circuit can output a target pulse signal with the target duty cycle under the control of the two target frequency control words. Because the control word providing circuit can generate the target frequency control words based on the desired target duty cycle, the pulse generation circuit can reliably generate the pulse signal with the target duty cycle based on the target frequency control words. In this way, the PWM circuit can flexibly generate the pulse signal.

The present disclosure provides a PWM circuit, a modulation method, and an electronic device, and relates to the field of communication technologies. In the PWM circuit, a control word providing circuit can generate, based on an obtained target duty cycle, two target frequency control words with a ratio of the target duty cycle, and output the two target frequency control words to a pulse generation circuit; and the pulse generation circuit can output a target pulse signal with the target duty cycle under the control of the two target frequency control words. Because the control word providing circuit can generate the target frequency control words based on the desired target duty cycle, the pulse generation circuit can reliably generate the pulse signal with the target duty cycle based on the target frequency control words. In this way, the PWM circuit can flexibly generate the pulse signal.

An electronic device has a modulator circuit, a pulse adjustment circuit, and a pulse generator circuit. The modulator circuit generates a comparator output signal based on a sensed inductor current signal of a power converter, an error amplifier output voltage signal, and a ramp signal to regulate an output voltage signal of the power converter. The pulse adjustment circuit generates an adjusted pulse signal based on the comparator output signal and the error amplifier output voltage signal, and to generate an adjusted clock signal based on an input clock signal and the error amplifier output voltage signal. The pulse generator circuit generates a switching control signal to control a transistor of the power converter based on the adjusted pulse signal and the adjusted clock signal.

An electronic device has a modulator circuit, a pulse adjustment circuit, and a pulse generator circuit. The modulator circuit generates a comparator output signal based on a sensed inductor current signal of a power converter, an error amplifier output voltage signal, and a ramp signal to regulate an output voltage signal of the power converter. The pulse adjustment circuit generates an adjusted pulse signal based on the comparator output signal and the error amplifier output voltage signal, and to generate an adjusted clock signal based on an input clock signal and the error amplifier output voltage signal. The pulse generator circuit generates a switching control signal to control a transistor of the power converter based on the adjusted pulse signal and the adjusted clock signal.

In a described example, a circuit includes a synchronization control circuit having a sync input and a sync control output, in which the sync input is coupled to a sync terminal configured to receive an external clock signal. An internal clock generator circuit has a control input and an output. The control input is coupled to the sync control output. An output circuit has first and second signal inputs, a mode control input and a clock output. The first signal input is coupled to the sync input, and the second signal input of the output circuit is coupled to the output of the internal clock generator circuit. The mode control input is coupled to the sync control output, and the clock output adapted to be coupled to a controller.

In a described example, a circuit includes a synchronization control circuit having a sync input and a sync control output, in which the sync input is coupled to a sync terminal configured to receive an external clock signal. An internal clock generator circuit has a control input and an output. The control input is coupled to the sync control output. An output circuit has first and second signal inputs, a mode control input and a clock output. The first signal input is coupled to the sync input, and the second signal input of the output circuit is coupled to the output of the internal clock generator circuit. The mode control input is coupled to the sync control output, and the clock output adapted to be coupled to a controller.