Aspects of the present disclosure related to a method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal. The method includes measuring one or more parameters of the clock signal, determining a duty-cycle adjustment based on the measured one or more parameters, and adjusting a duty cycle of the clock signal based on the determined duty-cycle adjustment.

Aspects of the present disclosure related to a method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal. The method includes measuring one or more parameters of the clock signal, determining a duty-cycle adjustment based on the measured one or more parameters, and adjusting a duty cycle of the clock signal based on the determined duty-cycle adjustment.

An oscillator circuit is provided. A first and a second cycle generating units, and a first and a second duty generating units are included. An SR latch, receiving outputs the first and second cycle generating units. In the SR latch, an output is provided to the first cycle generating unit and the third duty generating, and a contemporary output is provided to the second cycle generating unit and the second duty generating unit. A logic circuit receives the outputs of the first and the second duty generating units and the output and the contemporary output of the SR latch to generate a clock signal. The first and the second cycle generating units are respectively operated to provide the even and odd cycle times of the clock signal. The first and the second duty generating units are respectively operated to provide the even and odd duties of the clock signal.

An oscillator circuit is provided. A first and a second cycle generating units, and a first and a second duty generating units are included. An SR latch, receiving outputs the first and second cycle generating units. In the SR latch, an output is provided to the first cycle generating unit and the third duty generating, and a contemporary output is provided to the second cycle generating unit and the second duty generating unit. A logic circuit receives the outputs of the first and the second duty generating units and the output and the contemporary output of the SR latch to generate a clock signal. The first and the second cycle generating units are respectively operated to provide the even and odd cycle times of the clock signal. The first and the second duty generating units are respectively operated to provide the even and odd duties of the clock signal.

An ignition coil control system includes: a plurality of ignition coils that respectively include a primary coil and a secondary coil; a spark plug that generates a spark discharge by a discharge current generated by the plurality of ignition coils and that includes a center electrode and a ground electrode; a sensing part measuring a current applied to the primary coil; and an ignition controller that adjusts a reference duty signal based on an amount of the current applied to the primary coil sensed by the sensing part to adjust discharge energy generated between the center electrode and the ground electrode through the secondary coil.

An ignition coil control system includes: a plurality of ignition coils that respectively include a primary coil and a secondary coil; a spark plug that generates a spark discharge by a discharge current generated by the plurality of ignition coils and that includes a center electrode and a ground electrode; a sensing part measuring a current applied to the primary coil; and an ignition controller that adjusts a reference duty signal based on an amount of the current applied to the primary coil sensed by the sensing part to adjust discharge energy generated between the center electrode and the ground electrode through the secondary coil.

A semiconductor memory device includes a mode register set and a clock correction circuit. The mode register set stores a first control code set. During a duty training interval based on a duty training command, the clock correction circuit may divide the duty training interval into a first interval, a second interval and a third interval which are consecutive, may correct a phase skew of a first clock signal and a third clock signal during the first interval, may correct a phase skew of a second clock signal and a fourth clock signal during the second interval, and may correct a phase skew of the first clock signal and the fourth clock signal during the third interval. The semiconductor memory device may enhance signal integrity of clock signals by correcting duty errors and phase skews of the clock signals having multi-phases during the duty training interval.

A semiconductor memory device includes a mode register set and a clock correction circuit. The mode register set stores a first control code set. During a duty training interval based on a duty training command, the clock correction circuit may divide the duty training interval into a first interval, a second interval and a third interval which are consecutive, may correct a phase skew of a first clock signal and a third clock signal during the first interval, may correct a phase skew of a second clock signal and a fourth clock signal during the second interval, and may correct a phase skew of the first clock signal and the fourth clock signal during the third interval. The semiconductor memory device may enhance signal integrity of clock signals by correcting duty errors and phase skews of the clock signals having multi-phases during the duty training interval.

The technology of this application relates to a clock signal generator, an on-chip clock system, and a chip. The clock signal generator includes a first transistor, a second transistor, a flip-flop, and a power supply end. A first electrode of the first transistor and a first electrode of the second transistor are coupled to the power supply end, and a second electrode of the first transistor and a second electrode of the second transistor are coupled to a common ground. A first input end of the flip-flop is coupled to the first electrode of the first transistor, and a second input end of the flip-flop is coupled to the first electrode of the second transistor. The clock signal generator can make a frequency of an output clock signal more stable.

Embodiments of the present application provide an oscillator and a clock generation circuit. The oscillator includes: a first ring topology, including a plurality of first inverters connected end to end, and configured to transmit an oscillation signal at a first transmission speed; and a second ring topology, including a plurality of second inverters connected end to end, and configured to transmit the oscillation signal at a second transmission speed, wherein the present application, the first ring topology is electrically connected to the second ring topology, and the second transmission speed is less than the first transmission speed.