Embodiments of the present application provide an oscillator and a clock generation circuit. The oscillator includes: a first ring topology, including a plurality of first inverters connected end to end, and configured to transmit an oscillation signal at a first transmission speed; and a second ring topology, including a plurality of second inverters connected end to end, and configured to transmit the oscillation signal at a second transmission speed, wherein the present application, the first ring topology is electrically connected to the second ring topology, and the second transmission speed is less than the first transmission speed.

Provided are a clock signal production circuit, a clock signal production method, and an electronic device, relating to the technical field of communications. In the clock signal production circuit, by digital circuits such as a control word generation circuit, an initial clock generation circuit, and a spread spectrum clock generation circuit, a frequency control word is first generated on the basis of spread spectrum parameters, an initial clock signal of a target duty cycle is then generated on the basis of the frequency control word, and spread spectrum processing is finally performed on the basis of the target duty cycle of the initial clock signal and the frequency control word to obtain a spread spectrum clock signal, i.e., the entire spread spectrum process is executed by the digital circuits. Therefore, it is not necessary to control the electronic device comprising the clock signal production circuit to stop working, i.e., the normal operation of the electronic device is not affected. Moreover, according to the clock signal production circuit, real-time adjustment of spread spectrum parameters (such as spread spectrum depth) that affect a spread spectrum result can be implemented, and the spread spectrum flexibility is relatively high.

Provided are a clock signal production circuit, a clock signal production method, and an electronic device, relating to the technical field of communications. In the clock signal production circuit, by digital circuits such as a control word generation circuit, an initial clock generation circuit, and a spread spectrum clock generation circuit, a frequency control word is first generated on the basis of spread spectrum parameters, an initial clock signal of a target duty cycle is then generated on the basis of the frequency control word, and spread spectrum processing is finally performed on the basis of the target duty cycle of the initial clock signal and the frequency control word to obtain a spread spectrum clock signal, i.e., the entire spread spectrum process is executed by the digital circuits. Therefore, it is not necessary to control the electronic device comprising the clock signal production circuit to stop working, i.e., the normal operation of the electronic device is not affected. Moreover, according to the clock signal production circuit, real-time adjustment of spread spectrum parameters (such as spread spectrum depth) that affect a spread spectrum result can be implemented, and the spread spectrum flexibility is relatively high.

A duty margin monitoring circuit, coupled to a functional circuit which generates a first output signal in response to a target signal, includes a modulation circuit, a replica circuit and an error detection circuit. The modulation circuit is arranged to receive the target signal and modulate the target signal to generate a modulated target signal. The replica circuit is arranged to receive the modulated target signal and generate a second output signal in response to the modulated target signal. The error detection circuit is coupled to the functional circuit and the replica circuit to receive the first output signal and the second output signal and arranged to generate an error detection result according to the first output signal and the second output signal.

A duty margin monitoring circuit, coupled to a functional circuit which generates a first output signal in response to a target signal, includes a modulation circuit, a replica circuit and an error detection circuit. The modulation circuit is arranged to receive the target signal and modulate the target signal to generate a modulated target signal. The replica circuit is arranged to receive the modulated target signal and generate a second output signal in response to the modulated target signal. The error detection circuit is coupled to the functional circuit and the replica circuit to receive the first output signal and the second output signal and arranged to generate an error detection result according to the first output signal and the second output signal.

Disclosed is a device (10) for adjusting the quantity of two liquids that are aerosolised in order to be inhaled simultaneously by a user, characterised in that said device comprises: two tanks (105, 110), a first tank comprising a first liquid and a second tank comprising a second liquid having at least one different property, each liquid being configured to be aerosolised when this liquid undergoes a determined physical interaction; an end piece (115) for inhalation, by the user, of the aerosolised liquid coming from each tank, two aerosolisation means (120, 125) for aerosolising the first and second liquid respectively, each tank being associated with one aerosolisation means; a single autonomous source of electrical power (130) for supplying electrical power to each aerosolisation means, a means (135) for determining a ratio of liquids to be aerosolised for each liquid and a switching means (140) for alternately supplying each aerosolisation means with electrical power from the single autonomous power source, as a function of the determined ratio, the switching means comprising two pulse-width modulators installed in series or a single pulse-width modulator between the autonomous electrical power source and each aerosolisation means.

A semiconductor integrated circuit of an embodiment includes: a delay element array circuit in which a plurality of delay elements having a delay amount Tw are connected in series; a flip-flop group including a plurality of flip-flops each of which an input is connected to an output of a corresponding delay element; a delay element group configured to generate, from an input clock signal, a plurality of output clock signals each having a delay difference of a second delay amount smaller than the delay amount Tw; and a delay unit configured to set a third delay amount smaller than the second delay amount, and the delay element group and the delay unit are connected in series between an output terminal of an input signal CLK_DET and an input terminal of the flip-flop group.

A semiconductor integrated circuit of an embodiment includes: a delay element array circuit in which a plurality of delay elements having a delay amount Tw are connected in series; a flip-flop group including a plurality of flip-flops each of which an input is connected to an output of a corresponding delay element; a delay element group configured to generate, from an input clock signal, a plurality of output clock signals each having a delay difference of a second delay amount smaller than the delay amount Tw; and a delay unit configured to set a third delay amount smaller than the second delay amount, and the delay element group and the delay unit are connected in series between an output terminal of an input signal CLK_DET and an input terminal of the flip-flop group.

A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.

A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.