The system may include a digital-to-analog converter configured to convert a digital signal to an analog signal. The system may include sample/hold circuits configured to receive and store the analog signal. The system may include an address controller configured to regulate which sample/hold circuits propagate the analog signal. The sample/hold circuits may be configured to feed the analog signal to devices of a memory array. The system may include an output circuit configured to program the devices by comparing currents of the devices to a target current. In response to one or more of the currents of the devices being within a threshold range, the output circuit may discontinue programming the corresponding devices. In response to one or more of the currents of the devices not being within the threshold range, the output circuit may continue programming the corresponding devices.

A phase synchronization circuit includes: an oscillation circuit that includes a variable current generation unit that generates a variable current of a current amount corresponding to a control voltage and a fixed current generation unit that generates a fixed current of a current amount corresponding to a correction code and generates an output clock signal having a frequency corresponding to the total current amount of the variable current and the fixed current; a feedback circuit that generates a feedback clock signal based on the output clock signal; a control voltage generation circuit that generates the control voltage to make a frequency of the output clock signal become a desired frequency in a normal operation mode; and a correction code generation circuit that generates the correction code in a calibration mode, in which in the calibration mode, the control voltage generation circuit outputs a fixed one of the control voltage.

A phase synchronization circuit includes: an oscillation circuit that includes a variable current generation unit that generates a variable current of a current amount corresponding to a control voltage and a fixed current generation unit that generates a fixed current of a current amount corresponding to a correction code and generates an output clock signal having a frequency corresponding to the total current amount of the variable current and the fixed current; a feedback circuit that generates a feedback clock signal based on the output clock signal; a control voltage generation circuit that generates the control voltage to make a frequency of the output clock signal become a desired frequency in a normal operation mode; and a correction code generation circuit that generates the correction code in a calibration mode, in which in the calibration mode, the control voltage generation circuit outputs a fixed one of the control voltage.

A ratiometric current source circuit having a reduced temperature dependence is disclosed. An embodiment of the current source circuit includes a first divider circuit configured to generate a reference voltage using a voltage level of a power supply node and a second divider circuit including a first resistor with a first temperature coefficient and a second resistor with a second temperature coefficient. The first resistor is configured to generate a first current using an input voltage and the voltage level of the power supply node and the second resistor is configured to generate a second current using the input voltage. The embodiment further includes a buffer circuit configured to generate the input voltage using the reference voltage and generate an output current using a difference between the first current and the second current.

A ratiometric current source circuit having a reduced temperature dependence is disclosed. An embodiment of the current source circuit includes a first divider circuit configured to generate a reference voltage using a voltage level of a power supply node and a second divider circuit including a first resistor with a first temperature coefficient and a second resistor with a second temperature coefficient. The first resistor is configured to generate a first current using an input voltage and the voltage level of the power supply node and the second resistor is configured to generate a second current using the input voltage. The embodiment further includes a buffer circuit configured to generate the input voltage using the reference voltage and generate an output current using a difference between the first current and the second current.

According to one embodiment, a power supply circuit includes a smoothing capacitor that is charged with a charge current from an output transistor and outputs a voltage as an output voltage; a control loop that controls a conduction state of the output transistor depending on a difference value between the output voltage and a reference voltage; and a gain adjustment circuit that adjusts a gain of the control loop depending on magnitude of the charge current after the charge starts.

According to one embodiment, a power supply circuit includes a smoothing capacitor that is charged with a charge current from an output transistor and outputs a voltage as an output voltage; a control loop that controls a conduction state of the output transistor depending on a difference value between the output voltage and a reference voltage; and a gain adjustment circuit that adjusts a gain of the control loop depending on magnitude of the charge current after the charge starts.

Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

Various implementations described herein are related to a device having header circuitry with first transistors that are configured to receive a supply voltage and provide a dynamically biased voltage. The device may include reference generation circuitry having multiple amplifiers that are configured to receive the supply voltage and provide reference voltages based on the supply voltage. The device may include bias generation circuitry having second transistors configured to track changes in the dynamically biased voltage and adjust the dynamically biased voltage by generating bias voltages based on the reference voltages and by applying the bias voltages to the header circuitry so as to adjust the dynamically biased voltage.