A delay line includes a delay chain, a pulse generator generating a pulse based on a received input signal, and a delay chain control circuit. The delay chain control circuit has a first input receiving the pulse, a second input receiving output from a last element of the delay chain, and a selection input receiving a delayed version of the received input signal. The delay chain control circuit has an output coupled to provide input to a first element of the delay chain in response to the delayed version of the received input signal. An output selection circuit receives outputs from each element of the delay chain, counts assertions of the output of the last element of the delay chain and, in response to the count being equal to a desired count, passes a desired one of the outputs of the elements of the delay chain as output.

A smart method is provided for a low-current oscillatory circuitry. The circuitry comprises an oscillator and a microcontroller unit (MCU). The oscillator comprises a proportional-to-absolute-temperature circuit connecting to a low-voltage regulator. The low-voltage regulator connects to a PMOS diode array and a delay unit circuit. The PMOS diode array connects to the MCU. The delay unit circuit connects to the MCU and a voltage converter. The method includes a normal temperature compensation algorithm; a smart learning algorithm of extra-high temperature compensation; and an ultra-high temperature compensation algorithm. Thus, clock variations are compensated; output frequency is stable and not affected by voltage or temperature variations; and process variations are suppressed. When process variations appear, there are not be too many errors generated. Therefore, a timebase clock is provided with high accuracy, wide operating voltage range, wide operating temperature range, and low power consumption operation.

The disclosure discloses an RC oscillating circuit. A first end of a capacitor is grounded, a second end of the capacitor is connected to a charging path, a discharging path and a comparator, A first input end of a comparator is connected to first reference voltage. An output end of the comparator outputs a first output signal and is connected to a control end of the discharging path. The first reference voltage provides the flipped voltage of the comparator The first output signal forms an output clock signal. A first regulating circuit is configured to regulate the magnitude of the charging current and realize coarse frequency tuning. A second regulating circuit is configured to regulate the magnitude of the first reference voltage and realize fine frequency tuning. The disclosure has the advantages of low power consumption, fast start, high precision and wide tuning range.

Various embodiments of the present technology may comprise methods and apparatus for an amplifier circuit. Methods and apparatus for an amplifier circuit according to various aspects of the present invention may provide a first cross-connect circuit responsive to a first clock signal having a first phase and the third clock signal having a third phase. The amplifier circuit may provide a second cross-connect circuit responsive to a second clock signal having a second phase and a fourth clock signal having a fourth phase. The clock signals have a same frequency with offset phases.

A delay line includes a delay chain, a pulse generator generating a pulse based on a received input signal, and a delay chain control circuit. The delay chain control circuit has a first input receiving the pulse, a second input receiving output from a last element of the delay chain, and a selection input receiving a delayed version of the received input signal. The delay chain control circuit has an output coupled to provide input to a first element of the delay chain in response to the delayed version of the received input signal. An output selection circuit receives outputs from each element of the delay chain, counts assertions of the output of the last element of the delay chain and, in response to the count being equal to a desired count, passes a desired one of the outputs of the elements of the delay chain as output.

A delay line includes a delay chain, a pulse generator generating a pulse based on a received input signal, and a delay chain control circuit. The delay chain control circuit has a first input receiving the pulse, a second input receiving output from a last element of the delay chain, and a selection input receiving a delayed version of the received input signal. The delay chain control circuit has an output coupled to provide input to a first element of the delay chain in response to the delayed version of the received input signal. An output selection circuit receives outputs from each element of the delay chain, counts assertions of the output of the last element of the delay chain and, in response to the count being equal to a desired count, passes a desired one of the outputs of the elements of the delay chain as output.

Various embodiments of the present technology may comprise methods and apparatus for an amplifier circuit. Methods and apparatus for an amplifier circuit according to various aspects of the present invention may comprise a first cross-connect circuit configured to receive an input signal at an input terminal and transmit the input signal to an input stage circuit. The amplifier circuit may further comprise a second cross-connect circuit connected between the input stage circuit and an output stage circuit, and a voltage adjustment circuit connected to the input stage circuit. Each cross-connect circuit may comprise a plurality of switches.

An optical measurement system includes a photosensor that includes one or more photosensitive elements. Each of the photosensitive elements may generate signals when a photon is detected, and the number of photons detected for each photosensor may be accumulated in an integration register. The integration register may accumulate photon counts independent of a parallel data path that stores photon counts in time bins based on photon arrival times to form a histogram representation. The total photon count in the integration register can be used to estimate ambient background light and properly set signal thresholds for detecting reflected light signals represented in the histogram.

Provided is an output circuit including a logic circuit, a capacitor, a buffer circuit, and a driver circuit. When a clock signal is input and an enable signal is active, the logic circuit outputs a clock signal based on the clock signal. The buffer circuit receives a signal that is an output signal of the logic circuit via the capacitor. The driver circuit outputs a clock signal based on a signal that is an output signal of the buffer circuit. The logic circuit sets a signal to the same logic level as an input node of the buffer circuit when the enable signal is inactive.

Provided is an output circuit including a logic circuit, a capacitor, a buffer circuit, and a driver circuit. When a clock signal is input and an enable signal is active, the logic circuit outputs a clock signal based on the clock signal. The buffer circuit receives a signal that is an output signal of the logic circuit via the capacitor. The driver circuit outputs a clock signal based on a signal that is an output signal of the buffer circuit. The logic circuit sets a signal to the same logic level as an input node of the buffer circuit when the enable signal is inactive.