H03K3/26

Low power oscillator using flipped-gate MOS

Relax oscillation circuits have at least one comparison circuit that is structured with a flipped gate transistor and a normal MOS transistor wherein the two transistors having different threshold voltages. The relaxation oscillators are configured for charging and discharging capacitances between the threshold voltages of the flipped gate transistor and the normal MOS transistor by toggling the state of a latching circuit to control the charging and discharging of the capacitances.

ELECTRICAL STIMULATION DEVICES AND SYSTEMS FOR SAFELY OPERATING SUCH DEVICES

Portable high-voltage electrical stimulation devices and systems are disclosed that are scalable to utilize a minimal number of output channels to a large number of output channels. The devices and systems include a high-voltage power supply and output pulse circuitry comprising a plurality of output channel circuits. The electrical stimulation devices and systems disclosed herein also provide improved safety features, including an optional safety monitor.

PUSH-PULL OUTPUT DRIVER AND OPERATIONAL AMPLIFIER USING SAME
20200162043 · 2020-05-21 · ·

A voltage driver circuit for an output stage of an operational amplifier, or other circuits, includes a level shifter and an output driver including a source follower and a common source amplifier in a push-pull configuration. The level shifter generates a node voltage as a function of an input voltage on the input node. The output driver including a first transistor having a control terminal receiving the node voltage, and connected between a supply voltage and an output node, and a second transistor having a control terminal receiving the input voltage from the input node, and connected between the output node and a reference voltage, wherein the first and second transistors have a common conductivity type.

PUSH-PULL OUTPUT DRIVER AND OPERATIONAL AMPLIFIER USING SAME
20200162043 · 2020-05-21 · ·

A voltage driver circuit for an output stage of an operational amplifier, or other circuits, includes a level shifter and an output driver including a source follower and a common source amplifier in a push-pull configuration. The level shifter generates a node voltage as a function of an input voltage on the input node. The output driver including a first transistor having a control terminal receiving the node voltage, and connected between a supply voltage and an output node, and a second transistor having a control terminal receiving the input voltage from the input node, and connected between the output node and a reference voltage, wherein the first and second transistors have a common conductivity type.

Neuromuscular Stimulation Using Multistage Current Driver Circuit
20200155841 · 2020-05-21 ·

Neuromuscular stimulation is widely used for rehabilitation and movement assist devices, due to its safety, efficacy, and ease of operation. For repeatable and accurate muscular contractions, a voltage controlled current sources (VCCS) with high compliance is required. Conventional VCCS design requires high-voltage rated operational amplifiers, which are expensive and consume large power. Moreover, conventional stimulators are not viable for simultaneous stimulation of muscle synergies, as they require multiple VCCS operating at the same time. This invention presents a neuromuscular stimulator with a multistage driver circuit wherein, a VCCS connected to an output driving stage comprising of folded-cascode transistor buffers and a bidirectional current mirror circuit. The multistage driver circuit uses inexpensive low-voltage rated operational amplifiers that consume 95% less power. Additionally, we disclose a stimulation method wherein only a single current source drives several output drivers connected in series or parallel to simultaneously stimulate multiple muscles or muscle synergies.

Neuromuscular Stimulation Using Multistage Current Driver Circuit
20200155841 · 2020-05-21 ·

Neuromuscular stimulation is widely used for rehabilitation and movement assist devices, due to its safety, efficacy, and ease of operation. For repeatable and accurate muscular contractions, a voltage controlled current sources (VCCS) with high compliance is required. Conventional VCCS design requires high-voltage rated operational amplifiers, which are expensive and consume large power. Moreover, conventional stimulators are not viable for simultaneous stimulation of muscle synergies, as they require multiple VCCS operating at the same time. This invention presents a neuromuscular stimulator with a multistage driver circuit wherein, a VCCS connected to an output driving stage comprising of folded-cascode transistor buffers and a bidirectional current mirror circuit. The multistage driver circuit uses inexpensive low-voltage rated operational amplifiers that consume 95% less power. Additionally, we disclose a stimulation method wherein only a single current source drives several output drivers connected in series or parallel to simultaneously stimulate multiple muscles or muscle synergies.

Oscillator circuit, and related integrated circuit

An oscillator circuit including a ring oscillator and a reference current source is provided. The ring oscillator includes an odd number of inverter stages. Each inverter stage includes a first transistor having a first reference threshold that varies over temperature. The reference current source is configured to generate a plurality of currents, where a respective current is applied directly to the drain of a respective first transistor of a respective inverter stage. The reference current source includes a reference transistor that has a second reference threshold that varies over temperature; a resistor coupled between a gate and a source of the reference transistor; a second transistor having a source coupled to the gate of the reference transistor for generating a reference current that flows through the resistor to regulate a voltage of the resistor to the second threshold voltage; and a current mirror configured to generate the plurality of currents.

Active biquad filter with oscillator circuit

Certain aspects of the present disclosure are generally directed to a tunable active filter and a method of calibrating a tunable active filter. One example apparatus is a filter circuit that generally includes a resistor-capacitor (RC) topology tunable active filter comprising a first amplifier, a second amplifier, and a feedback path coupled between an input of the first amplifier and an output of the second amplifier. The filter circuit also includes a negative transconductance circuit coupled to a first node of the tunable active filter.

RC oscillator with comparator offset compensation
10601407 · 2020-03-24 · ·

A comparator-based oscillator generates an output frequency that is relatively independent of comparator offset voltages. Charging/discharging circuitry controls the comparator input voltage, and logic circuitry generates the oscillator output (e.g., clock) signal and controls the charging/discharging circuitry. During an oscillator charging cycle, the charging/discharging circuitry drives the voltage at the comparator input node from a relatively low initial charging voltage level up to the comparator reference voltage. During an oscillator discharging cycle, the charging/discharging circuitry drives the voltage at the comparator input node from a relatively high initial discharging voltage level down to the comparator reference voltage. The initial charging and discharging voltage levels depend on the comparator reference voltage, such that a comparator offset voltage directly affects the initial charging and discharging voltage levels, thereby keeping the output frequency relatively unchanged.

Current-mode logic latches for a PVT-robust mod 3 frequency divider

An illustrative digital latch includes: a differential transistor pair (track pair) capacitively coupled to a differential input signal to cause a differential output voltage between output nodes to track the differential input signal when a clock signal is asserted; a cross-coupled transistor pair (latch pair) coupled to the output nodes to latch the differential output voltage when the clock signal is de-asserted; a differential transistor pair (clock pair) that steers a bias current between the track pair and the latch pair; and a matched set of bias transistors that determines the bias current for the clock pair and a reference voltage on a reference voltage node, the reference voltage node being coupled to a base of each transistor in the track pair by equal bias resistances.