H03K3/35

CAMERA LIGHTING POWER SUPPLY
20200323060 · 2020-10-08 ·

A pulsed power supply system for a vehicle vision sensor lighting device includes a pulsed power supply generator configured to electrically supply the lighting device, a linear DC voltage regulator configured to deliver a stabilized electrical voltage to the pulsed power supply generator from a variable electrical power source, and an amplifier configured to deliver an amplified electric current from the linear DC voltage regulator to the pulsed power supply generator.

CAMERA LIGHTING POWER SUPPLY
20200323060 · 2020-10-08 ·

A pulsed power supply system for a vehicle vision sensor lighting device includes a pulsed power supply generator configured to electrically supply the lighting device, a linear DC voltage regulator configured to deliver a stabilized electrical voltage to the pulsed power supply generator from a variable electrical power source, and an amplifier configured to deliver an amplified electric current from the linear DC voltage regulator to the pulsed power supply generator.

Electronic latch, a method for an electronic latch, a frequency division by two and a 4-phase generator

The present invention relates to an electronic latch circuit, a method, and a 4-phase generator. The electronic latch circuit comprises an output circuit comprising an output X, and an output Y. The electronic latch circuit further comprises an input circuit, comprising an input A, an input B, and a clock signal input. The input circuit is connected to the output circuit, and configured to select a state of the output circuit from the group of a first state, a second state, and a third state. The input circuit is further configured to select the first state upon detecting a high state on the input B, a transition on the clock signal input from a low state to a high state, and a low state on the input A, and that the electronic latch circuit is in the second state. The input circuit is further configured to select the second state upon detecting a high state on the input A, a low state on the input B, a low state on the clock signal input, and that the electronic latch circuit is in the first state; The input circuit is further configured to select the third state upon detecting a high state on the input A, a transition on the clock signal input from a low state to a high state, and a low state on the input B, and that the electronic latch circuit is in the second state. The input circuit is further configured to select the second state upon detecting a high state on the input A, a low state on the input B, a low state on the clock signal input, and that the electronic latch circuit is in the first state.

Precursor derived semiconductor devices having PN junctions

Methods of making various fibers are provided including co-axial fibers with oppositely doped cladding and core are provide; hollow core doped silicon carbide fibers are provided; and doubly clad PIN junction fibers are provided. Additionally methods are provided for forming direct PN junctions between oppositely doped fibers are provided. Various thermoelectric generators that incorporate the aforementioned fibers are provided.

Sequential circuit and operating method thereof

In a sequential circuit, a first stage is configured to charge a voltage of a first node in response to a clock, and to discharge the voltage of the first node in response to the clock, a voltage of a second node, and data; a second stage is configured to charge the voltage of the second node in response to the clock, and to discharge the voltage of the second node in response to the clock and a logic signal; a combinational logic is configured to generate the logic signal based on the voltage of the first node, the voltage of the second node, and the data; and a latch circuit is configured to latch the voltage of the second node in response to the clock.

Schmitt trigger circuit with hysteresis determined by modified polysilicon gate dopants
09935618 · 2018-04-03 · ·

A Schmitt trigger's hysteresis is established by standard and non-standard MOSFETs having different (lower/higher) threshold voltages. For example, a standard n-channel transistor having a relatively low threshold voltage (e.g., 1V) sets the lower trigger switching voltage, and a non-standard n-channel transistor (e.g., an n-channel source/drain and a polysilicon gate doped with a p-type dopant) exhibits a relatively high threshold voltage (e.g., 2V) that sets the higher trigger switching voltage. An output control circuit generates the Schmitt trigger's digital output signal based on the on/off states of the two (non-standard and standard) MOSFETs, whereby the changes digital output signal between two values when the analog input signal falls below the lower threshold voltage (i.e., when both MOSFETs are turned on/off) and rises above the higher threshold voltage (i.e., when both MOSFETs are turned off/on). Self-resetting and other circuits utilize the Schmitt trigger to facilitate, e.g., high dynamic range image sensor pixels.

High speed voltage level shifter

In one embodiment, a voltage level shifter includes a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output. The voltage level shifter also includes a second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.

Area-optimized retention flop implementation

An integrated circuit device having a p-well plane, a plurality of substantially parallel n-well rows, and a logic cell. The p-well plane is comprised of p-type semiconductor material. Each n-well row comprises an n-type layer disposed on the surface of the p-well plane. The plurality of n-well rows includes a first n-well row and a second n-well row. The logic cell is arranged on the p-well plane and the footprint of the logic cell encompasses both the first and second n-well rows.

Processing apparatus
12263673 · 2025-04-01 · ·

A processing apparatus comprises: an integrated circuit; a power supply unit connected to an external power supply and configured to perform power supply to the integrated circuit; and a power switch configured to switch a state of the processing apparatus based on power supplied from the power supply unit. The integrated circuit comprises a control unit configured to control a power state of the integrated circuit in a state in which power supply to the integrated circuit is being performed by the power supply unit.

Processing apparatus
12263673 · 2025-04-01 · ·

A processing apparatus comprises: an integrated circuit; a power supply unit connected to an external power supply and configured to perform power supply to the integrated circuit; and a power switch configured to switch a state of the processing apparatus based on power supplied from the power supply unit. The integrated circuit comprises a control unit configured to control a power state of the integrated circuit in a state in which power supply to the integrated circuit is being performed by the power supply unit.