Patent classifications
H03K3/353
LOW VOLTAGE DETECTION CIRCUIT, NONVOLATILE MEMORY APPARATUS INCLUDING THE SAME, AND OPERATING METHOD THEREOF
A low voltage detection circuit includes a first detection block configured to detect a level of an external voltage according to a reference voltage, and output a pre-detection signal; and a second detection block configured to generate a low voltage detection signal of a beginning level regardless of a variation in a level of the pre-detection signal when the level of the pre-detection signal is detected as the beginning level.
Nanosecond pulsed power sources having multi-core transformers
Described herein are apparatuses and methods for applying high voltage, sub-microsecond (e.g., nanosecond range) pulsed output to a biological material, e.g., tissues, cells, etc., using a high voltage (e.g., MOSFET) gate driver circuit having a high voltage isolation and a low inductance. In particular, described herein are multi-core pulse transformers comprising independent transformer cores arranged in parallel on opposite sides of a substrate. The transformer cores may have coaxial primary and secondary windings. Also describe are pulse generators including multi-core pulse transformers arranged in parallel (e.g., on opposite sides of a PCB) to reduce MOSFET driver gate inductance.
Nanosecond pulsed power sources having multi-core transformers
Described herein are apparatuses and methods for applying high voltage, sub-microsecond (e.g., nanosecond range) pulsed output to a biological material, e.g., tissues, cells, etc., using a high voltage (e.g., MOSFET) gate driver circuit having a high voltage isolation and a low inductance. In particular, described herein are multi-core pulse transformers comprising independent transformer cores arranged in parallel on opposite sides of a substrate. The transformer cores may have coaxial primary and secondary windings. Also describe are pulse generators including multi-core pulse transformers arranged in parallel (e.g., on opposite sides of a PCB) to reduce MOSFET driver gate inductance.
CSAMT transmitter
The present invention discloses a CSAMT transmitter, including: a first transmitter, where the first transmitter includes a first generator, a first rectifier module, a first transmission module, and a second transmission module, the first generator is connected to the first transmission module and the second transmission module by using the first rectifier module; and a second transmitter, where the second transmitter includes a second generator, a second rectifier module, a third transmission module, and a fourth transmission module, the second generator is connected to the third transmission module and the fourth transmission module by using the second rectifier module, where the first transmission module is connected to the third transmission module, and the second transmission module is connected to the fourth transmission module; the first transmission module has the same voltage as the third transmission module, and the second transmission module has the same voltage as the fourth transmission module.
CSAMT transmitter
The present invention discloses a CSAMT transmitter, including: a first transmitter, where the first transmitter includes a first generator, a first rectifier module, a first transmission module, and a second transmission module, the first generator is connected to the first transmission module and the second transmission module by using the first rectifier module; and a second transmitter, where the second transmitter includes a second generator, a second rectifier module, a third transmission module, and a fourth transmission module, the second generator is connected to the third transmission module and the fourth transmission module by using the second rectifier module, where the first transmission module is connected to the third transmission module, and the second transmission module is connected to the fourth transmission module; the first transmission module has the same voltage as the third transmission module, and the second transmission module has the same voltage as the fourth transmission module.
Ultra-low energy per cycle oscillator topology
In described examples of an integrated circuit (IC), an oscillator includes Schmitt trigger delay cells connected in a ring topology. The Schmitt trigger delay cells have a high input threshold approximately equal to Vdd and a low input threshold approximately equal to Vss to increase delay through each cell. An output buffer receives a phase signal from an output terminal of one of the Schmitt trigger delay cells and converts a transition phase signal to a faster transition clock signal. The output buffer has control circuitry that generates non-overlapping control signals in response to the phase signal, to control an output stage to generate the fast transition clock signal while preventing short circuit current in the output stage.
Ultra-low energy per cycle oscillator topology
In described examples of an integrated circuit (IC), an oscillator includes Schmitt trigger delay cells connected in a ring topology. The Schmitt trigger delay cells have a high input threshold approximately equal to Vdd and a low input threshold approximately equal to Vss to increase delay through each cell. An output buffer receives a phase signal from an output terminal of one of the Schmitt trigger delay cells and converts a transition phase signal to a faster transition clock signal. The output buffer has control circuitry that generates non-overlapping control signals in response to the phase signal, to control an output stage to generate the fast transition clock signal while preventing short circuit current in the output stage.
Low powered clock driving
A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.
Low powered clock driving
A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.
Nanosecond pulsed power sources having multi-core transformers
Described herein are apparatuses and methods for applying high voltage, sub-microsecond (e.g., nanosecond range) pulsed output to a biological material, e.g., tissues, cells, etc., using a high voltage (e.g., MOSFET) gate driver circuit having a high voltage isolation and a low inductance. In particular, described herein are multi-core pulse transformers comprising independent transformer cores arranged in parallel on opposite sides of a substrate. The transformer cores may have coaxial primary and secondary windings. Also describe are pulse generators including multi-core pulse transformers arranged in parallel (e.g., on opposite sides of a PCB) to reduce MOSFET driver gate inductance.