Disclosed is a device for detecting the margin of a circuit operating at an operating speed. The device includes: a signal generating circuit generating an input signal including predetermined data; a first adjustable delay circuit delaying the input signal by a first delay amount and thereby generating a delayed input signal; a circuit under test performing a predetermined operation based on a predetermined operation timing and thereby generating a to-be-tested signal according to the delayed input signal; a second adjustable delay circuit delaying the to-be-tested signal by a second delay amount and thereby generating a delayed to-be-tested signal; a comparison circuit comparing the data included in the delayed to-be-tested signal with the predetermined data based on the predetermined operation timing and thereby generating a comparison result; and a calibration circuit determining whether the circuit under test passes a speed test according to the comparison result.

A delay element including a first set of field effect transistors (FETs) with gates configured to receive a first control voltage; a second set of FETs coupled in series with the first set of FETs between a first voltage rail and a first node, respectively, the second set of FETs include gates configured to receive a set of complementary select signals, respectively; a third set of FETs including gates configured to receive a set of non-complementary select signals, respectively; a fourth set of FETs coupled in series with the third set of FETs between a second node and a second voltage rail, respectively, the fourth set of FETs including gates configured to receive a second control voltage; and an inverter coupled between the first node and the second node, the inverter including an input configured to receive an input signal and an output configured to produce an output signal.

A circuit system is disclosed. In one example, the circuit system includes a clock tree circuit with multiple lanes to which a clock signal is distributed. A duty correction circuit is provided for each of the multiple lanes, and corrects a duty ratio of the clock signal. A clock gating circuit group has a clock gating circuit for each of the multiple lanes and receives, as input, the clock signal from the duty correction circuit. The clock gating circuit group starts output of the clock signal from each of a plurality of the clock gating circuits in a predetermined period. A variable delay circuit is provided in association with each of a plurality of the duty correction circuits and is capable of changing a delay time of a control signal that controls a timing of starting output of the clock signal from the clock gating circuit.

A voltage-controlled delay line including a clipper configured to produce a clipped input voltage from an input voltage, an oscillator configured to produce a strobe pulse train that is initiated by the clipped input voltage, and a divider module configured to divide the strobe pulse train and produce an output voltage from the divided strobe pulse train.

A quadrature clock generator includes a variable delay clock generator configured to receive a first clock and a third clock and output a second clock and a fourth clock in accordance with a control signal, wherein the first clock and the third clock are substantially the same but offset in timing by one half of the period; a quadrature phase error detector configured to receive the first clock, the second clock, the third clock, and the fourth clock and output a first phase detection signal and a second phase detection signal, wherein the first phase detection signal represents a relative timing between the first clock and the second clock and the second phase detection signal represents a relative timing between the second clock and the third clock; and an amplifier configured to amplify a difference between the first phase detection signal and the second phase detection signal into the control signal.

In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

A device is provided for jamming electromagnetic radiation liable to be emitted by at least one portion of an interconnect region located above at least one zone of an integrated electronic circuit produced in and on a semiconductor substrate. The device includes an antenna located above the at least one zone of the circuit and generating circuit coupled to the antenna and configured to generate an electrical signal having at least one pseudo-random property to pass through the antenna.

A signal recovery circuit includes a clock code generation circuit configured to generate codes in response to an enable signal and a clock, and a pulse recovery circuit configured to generate an output pulse in response to an input pulse and the codes.

A reference current generating circuit has a variable current supply to output a reference current, delay circuitry to generate a reference clock by delaying a clock by a reference delay amount and a delay clock by delaying the clock depending on a current value of the reference current, a phase comparator to compare a phase of the reference clock with a phase of the delay clock to output a comparison result, and control circuitry to control the current value of the reference current based on the compared result.

A circuit includes a first switch, a second switch, a first delay circuit and a second delay circuit. The first switch includes a first terminal, and the second switch includes a second terminal. The first delay circuit is coupled to the first terminal and the second terminal. The first delay circuit is configured to alternately turn ON the first switch and the second switch in accordance with an input signal and with a delay between successive ON times of the first switch and the second switch. The second delay circuit is coupled to the first terminal and the second terminal. The second delay circuit is configured to control the first delay circuit to generate the delay in accordance with a stored setting of the delay, a first voltage on the first terminal, or a second voltage on the second terminal.