A desaturation protection circuit is provided. Aspects includes a main gate driver circuit driving a gate for a switch, a desaturation gate driver circuit coupled to a drain terminal of the switch, a PWM signal supply circuit configured to supply a PWM signal to the desaturation gate driver circuit, and a delay circuit, the delay circuit configured to delay the PWM signal from the PWM signal supply circuit to the desaturation gate driver circuit during a turn-on event for the switch.

A detection circuit for detecting a clock signal includes a multiplexer, a digital-to-analog converter, a comparator, and a counter. The multiplexer outputs either a first signal or a second signal as a selection signal. The digital-to-analog converter outputs a reference voltage according to the selection signal. The comparator compares the clock signal to the reference voltage to generate a comparison signal. The counter counts a reference clock signal to generate an overflow signal, and resets the overflow signal according to the comparison signal. The overflow signal indicates the amplitude of the clock signal.

A delay circuit applies a one sample delay to a first digital sinusoid signal and outputs a delayed digital sinusoid signal. The first digital sinusoid signal and the delayed digital sinusoid signal are then added to each other by an adder circuit to generate an added digital sinusoid signal. A gain scaling circuit applies a scaling factor to the added digital sinusoid signal to generate a second digital sinusoid signal. Samples of the first and second digital sinusoid signals are alternately selected by a multiplexing circuit to generate a third digital sinusoid signal having twice as many samples as the first digital sinusoid signal over a same sinusoid period.

A pulse stretcher is disclosed comprising, a stretcher input (10) and a stretcher output (20); an asynchronous finite state machine; and a delay generator (40) having a delay input connected to the stretcher output, and a delay output connected to a second input of the FSM. The asynchronous FSM comprises: a first Muller C-element gate (250) having an output connected to the stretcher output, a second Muller C-element gate (260) having an output; and a combinatorial logic circuit (270) connected to the stretcher input, to first and second inputs of each of the first and second C-elements. The first and second Muller C-element gates are cross-coupled via the combinatorial logic, such that the respective outputs of the C-element gates are complementary and, in response to receiving the input pulse at the stretcher input, the output of the first Muller C-element gate provides a stretched version of the input pulse.

A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.

A circuit for setting a threshold level for extracting data from a signal stream includes a terminal couplable to the signal stream. A peak detector is coupled to the terminal. A valley detector is coupled to the terminal. A comparator is coupled to outputs of the peak detector and the valley detector for generating a threshold voltage for extracting data or commands from the signal stream. A method of extracting data from a signal stream including: peak detecting the signal stream to generate a first signal; valley detecting the signal stream to generate a second signal; combining the first and second signals to generate a threshold signal; and extracting data from the signal stream utilizing the threshold level signal.

A delay circuit applies a one sample delay to a first digital sinusoid signal and outputs a delayed digital sinusoid signal. The first digital sinusoid signal and the delayed digital sinusoid signal are then added to each other by an adder circuit to generate an added digital sinusoid signal. A gain scaling circuit applies a scaling factor to the added digital sinusoid signal to generate a second digital sinusoid signal. Samples of the first and second digital sinusoid signals are alternately selected by a multiplexing circuit to generate a third digital sinusoid signal having twice as many samples as the first digital sinusoid signal over a same sinusoid period.

A voltage regulator circuit includes a high side (HS) transistor having a control input and a low side (LS) transistor having a control input. The LS transistor is coupled to the HS transistor at a switching terminal. A comparator has first and second inputs and an output. A first resistor is coupled to the switching terminal. A second resistor is coupled between the first resistor and the second input of the comparator. A capacitor is coupled between a second resistor terminal of the second resistor and ground. A switch has first and second switch terminals and a control input. The first switch terminal is coupled to the first resistor terminal of the second resistor, and the second switch terminal is coupled to the second resistor terminal. A delay circuit has an input and an output. The output of the delay circuit is coupled to the control input of the switch.

An improved circuit or method generates first and second initial pulses that do not overlap. First and second drive pulses are generated based on the first and second initial pulses, respectively. A first transistor is turned on with the first drive pulses. A second transistor is turned on with the second drive pulses. A current flows in response to an on-time state of the first transistor overlapping with an on-time state of the second transistor. A delay of the second drive pulses is decreased based on a time of the current flow overlapping with one of the first initial pulses; and the delay of the second drive pulses is increased based on the time of the current flow overlapping with one of the second initial pulses.

A jitter generator may include a duty cycle code generator that generates a duty cycle control signal and an input buffer that outputs a signal based on its duty cycle. The input buffer may be coupled to the duty cycle code generator and to a source of a clock signal. After receiving the clock signal, the input buffer outputs the clock signal having jitter relative to the clock signal received from the source. The jitter may be added at least in part by components of the input buffer offsetting different transitions of the clock signal according to the duty cycle. Jitter may be added when the duty cycle changes in response to changes in the duty cycle control signal, such as in response to number generator circuitry of the duty cycle code generator update its output number, in response to a mode change received from a controller, or the like.