Certain aspects of the present disclosure provide an apparatus for noise cancellation. One example apparatus generally includes a first delay path and a second delay path, each providing signals generated by applying a different delay to an input signal, and a first comparator having a first input coupled to the first delay path and a second input coupled to the second delay path. The apparatus also includes a switching circuit having a control input coupled to an output of the first comparator, the switching circuit configured to selectively couple the first delay path or the second delay path to an output node of the switching circuit based on a signal at the control input. The apparatus also includes an attenuation circuit having a first input coupled to an input path for providing the input signal, and a second input coupled to the output node of the switching circuit.

A delay circuit includes: a delay line that delays an input signal in accordance with a delay setting signal and performs output of the input signal as a delayed signal; and a logic circuit processes the input signal to the delay line and the delayed signal.

Switch comprising at least one PCM portion that can be in a conducting or blocked state depending on the amorphous or crystalline state of the PCM that can change state when it is heated, in which the PCM portion is continuous and has an elongated shape such that an input and an output of the switch are connected to two ends of the PCM portion respectively that are separated from each other by a distance corresponding to the largest dimension of the PCM portion, and comprising a control device of the state of the switch capable of passing heating currents through the PCM portion, approximately perpendicular to the largest dimension of the PCM portion, from at least two input points separated from each other and separated from the ends of the PCM portion, to at least two output points separated from each other and separated from the ends of the PCM portion.

Switch comprising at least one PCM portion that can be in a conducting or blocked state depending on the amorphous or crystalline state of the PCM that can change state when it is heated, in which the PCM portion is continuous and has an elongated shape such that an input and an output of the switch are connected to two ends of the PCM portion respectively that are separated from each other by a distance corresponding to the largest dimension of the PCM portion, and comprising a control device of the state of the switch capable of passing heating currents through the PCM portion, approximately perpendicular to the largest dimension of the PCM portion, from at least two input points separated from each other and separated from the ends of the PCM portion, to at least two output points separated from each other and separated from the ends of the PCM portion.

Various implementations described herein are related to a device having adaptive clocking architecture with multiple stages of latches and buffers coupled in a delay line configuration. In some instances, each latch receives a delayed clock signal as data input and provides a sample out signal as a latched output based on a clock signal. Also, in some instances, each latch provides a delayed edge of a next clock cycle so as to stretch the pulse width of the clock signal.

The present invention provides a delay locked loop (DLL) that can complete the process of adjusting the delay of an internal clock signal within a predetermined execution period. The DLL includes a DLL control circuit and a delay line circuit. The DLL control circuit sets the delay amount based on the phase difference between an input clock signal and an output clock signal. The delay line circuit performs a delay operation on the input clock signal according to the delay amount, thereby generating the output clock signal. The delay line circuit includes a plurality of delay units, each delay unit includes at least one delay element, and one of the delay units includes a greater number of delay elements than another delay unit.

A delay circuit includes: a delay line that delays an input signal in accordance with a delay setting signal and performs output of the input signal as a delayed signal; and a logic circuit that performs logical calculation of the input signal to the delay line and the delayed signal.

An integrated circuit includes a programmable reflective load line that includes main delay segments arranged in series between an input of the programmable reflective load line and ground, variable delay modules arranged in parallel between nodes adjoining the main delay segments and ground, and main switches, with each main switch arranged between one of the variable delay modules and one of the nodes adjoining the main delay segments. Each variable delay module includes sub-delay segments arranged in series between the associated main switch and ground. Each variable delay module also includes one or more sub-delay switches, with each sub-delay switch arranged between a node adjoining two of the associated sub-delay segments and ground. The integrated circuit may further include a hybrid coupler arranged with the programmable reflective load line and another programmable reflective load line as a reflective-type phase-shifter.

In an embodiment, a circuit includes cascaded delay units arranged in a chain, each delay unit having an input-to-output delay time, wherein a first delay unit in the chain is configured to receive an input signal for propagating along the delay units in the chain, logic circuitry coupled to delay units in the chain, the logic circuitry configured to generate a clock signal as a logic combination of signals input to and output from the delay units in the chain and feedback circuitry configured to supply to the first delay unit in the chain a feedback signal, the feedback circuitry including a first feedback signal path from a last delay unit in the chain to the first delay unit in the chain and a second feedback signal path from an intermediate delay unit in the chain to the first delay unit in the chain, the intermediate delay unit arranged between the first delay unit in the chain and the last delay unit in the chain.

A driver circuit includes a flipflop and a first plurality of series-coupled delay elements. The flipflop may be configured to encode a sequence of codewords in a multibit signal. The first plurality of series-coupled delay elements may be configured to propagate the multibit signal to a tuning circuit in the driver circuit during voltage ramping of a power supply used by the driver circuit. Each codeword in the sequence of codewords may be used to configure the tuning circuit during the voltage ramping of the power supply. The sequence of codewords may be configured to incrementally change impedance of the driver during the voltage ramping of the power supply.