In an embodiment, a method for operating a plurality of delay units include supplying to a first delay unit in a chain an input signal that propagates along delay units in the chain, generating a clock signal as a logic combination of signals input to and output from delay units in the chain and forwarding a feedback signal to the first delay unit in the chain via a first feedback signal path from a last delay unit in the chain to the first delay unit in the chain and a second feedback signal path from an intermediate delay unit in the chain to the first delay unit in the chain, the intermediate delay unit being arranged between the first delay unit and the last delay unit.

A power-up initialization circuit includes a delay chain circuit and a signal generator circuit. The delay chain circuit receives a power supply voltage, and applies a predetermined delay amount to the power supply voltage for generating a delayed output voltage. The signal generator circuit receives the delayed output voltage from the delay chain circuit, and generates and outputs at least one power-up initialization signal in response to the delayed output voltage.

A driver circuit includes a flipflop and a first plurality of series-coupled delay elements. The flipflop may be configured to encode a sequence of codewords in a multibit signal. The first plurality of series-coupled delay elements may be configured to propagate the multibit signal to a tuning circuit in the driver circuit during voltage ramping of a power supply used by the driver circuit. Each codeword in the sequence of codewords may be used to configure the tuning circuit during the voltage ramping of the power supply. The sequence of codewords may be configured to incrementally change impedance of the driver during the voltage ramping of the power supply.

An integrated circuit includes a programmable reflective load line that includes main delay segments arranged in series between an input of the programmable reflective load line and ground, variable delay modules arranged in parallel between nodes adjoining the main delay segments and ground, and main switches, with each main switch arranged between one of the variable delay modules and one of the nodes adjoining the main delay segments. Each variable delay module includes sub-delay segments arranged in series between the associated main switch and ground. Each variable delay module also includes one or more sub-delay switches, with each sub-delay switch arranged between a node adjoining two of the associated sub-delay segments and ground. The integrated circuit may further include a hybrid coupler arranged with the programmable reflective load line and another programmable reflective load line as a reflective-type phase-shifter.