A comparator circuit includes a comparator, a first selection circuit, and a switched-capacitor circuit. The comparator has a first terminal, a second terminal, and an output terminal. The comparator is configured to generate an output signal at the output terminal based on a first signal on the first terminal and a second signal on the second terminal. The first selection circuit is coupled with the first terminal of the comparator and configured to selectively set a first input signal or a first calibration signal as the first signal in response to a control signal. The switched-capacitor circuit is coupled with the output terminal and the second terminal of the comparator. The switched-capacitor circuit is configured to adjust and output the second signal based on the output signal.

A pulse current generation circuit (100) for neural stimulation includes an analogue signal receiving device (101) for receiving an analogue signal; an analogue-to-digital converter (102) for converting the analogue signal into a digital control signal; a current signal controller (103) for producing, according to the digital control signal, pulse current parameters for generating bidirectional pulse current signals; and a current generator (104) for generating, according to the pulse current parameters, bidirectional pulse current signals for neural stimulation, and the current generator can generate pulse currents of different precisions according to the pulse current parameters. In addition, the present invention further relates to a charge compensation circuit, a charge compensation method, and an implantable electrical retina stimulator using the pulse current generation circuit or the charge compensation circuit.

A pulse current generation circuit (100) for neural stimulation includes an analogue signal receiving device (101) for receiving an analogue signal; an analogue-to-digital converter (102) for converting the analogue signal into a digital control signal; a current signal controller (103) for producing, according to the digital control signal, pulse current parameters for generating bidirectional pulse current signals; and a current generator (104) for generating, according to the pulse current parameters, bidirectional pulse current signals for neural stimulation, and the current generator can generate pulse currents of different precisions according to the pulse current parameters. In addition, the present invention further relates to a charge compensation circuit, a charge compensation method, and an implantable electrical retina stimulator using the pulse current generation circuit or the charge compensation circuit.

In an embodiment, a buffer circuit may includes a current source circuit, a self-bias generation circuit, a signal input circuit, and a first current sink circuit. The current source circuit may apply current to a first node and a second node in response to a self-bias voltage. The self-bias generation circuit may generate the self-bias voltage which has a voltage level between voltage levels of the first and second nodes. The signal input circuit may control the voltage levels of the first node and the second node in response to a first input signal and a second input signal. The first current sink circuit may control an amount of current flowing from the signal input circuit to a ground terminal in response to an enable signal and the self-bias voltage.

A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

A routing integrated circuit element is disclosed. The routing integrated circuit element is connected between a first and a second electronic module and includes a body, a first, and a second buffer element. A first side of the body is connected to the first electronic module. A second side is connected to the second electronic module and located on a different side from the first side. The distance between the second side and the second electronic module is shorter than the distance between the second side and the first electronic module. The first buffer element transmits an electronic signal from the first side to the second side. The second buffer element transmits the electronic signal from the second side to the first side, wherein the transmission directions of the electronic signals transmitted by the first buffer element and the second buffer element are opposite.

A routing integrated circuit element is disclosed. The routing integrated circuit element is connected between a first and a second electronic module and includes a body, a first, and a second buffer element. A first side of the body is connected to the first electronic module. A second side is connected to the second electronic module and located on a different side from the first side. The distance between the second side and the second electronic module is shorter than the distance between the second side and the first electronic module. The first buffer element transmits an electronic signal from the first side to the second side. The second buffer element transmits the electronic signal from the second side to the first side, wherein the transmission directions of the electronic signals transmitted by the first buffer element and the second buffer element are opposite.

Provided are a switching regulator and a voltage-current conversion circuit configured to shorten a start-up period. The voltage-current conversion circuit includes: a first MOS transistor of a first conductivity type including a gate and a drain connected in common, and a source connected to a first power supply terminal; a first resistor connected between the drain of the first MOS transistor and a second power supply terminal; and a correction current generation unit including a second resistor, and configured to generate, as a correction current, through use of the second resistor, a current corresponding to a current generated when a voltage corresponding to an absolute value of a gate-source voltage of the first MOS transistor is applied to the first resistor. The voltage-current conversion circuit is configured to add the correction current to a current flowing through the first resistor, to thereby generate the conversion current.

A circuit having a first, second, and third capacitor. Capacitor plates of the capacitors are connected to a first circuit node. The circuit supplies a first time-dependent voltage to the first capacitor, a second time-dependent voltage to the second capacitor, and a third time-dependent voltage to the third capacitor. The first and second voltages are clocked in antiphase. The second and third voltages are clocked in phase. The circuit has an amplifier, a synchronous demodulator, and a comparator. Inputs of the amplifier are connected to the first circuit node and ground. The synchronous demodulator alternately applies an output signal of the amplifier to inputs of the comparator, synchronously with the clock frequency of the first voltage. The circuit generates a control value dependent on an output of the comparator. The circuit changes amplitudes of the first and third voltage and/or the second voltage dependent on the control value.