Some examples relate to a system including a pulse modulation (PM) circuit having a PM input and a PM output. The system also includes a load circuit having a load circuit input, and an I/O pad coupling the PM output to the load circuit input. An asymmetry detection circuit has a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input of the pulse modulation circuit via a control path.

A photodetection device according to the present disclosure includes: a pixel; a reference signal generation unit; a comparison circuit; and a first switch. The pixel is configured to generate a pixel signal. The reference signal generation unit is configured to generate a reference signal. The comparison circuit includes a first-stage amplifier circuit and a second-stage amplifier circuit that is coupled to the first-stage amplifier circuit through a connection node. The first-stage amplifier circuit is configured to output a first output signal corresponding to a comparison operation based on the pixel signal and the reference signal. The second-stage amplifier circuit is configured to output a second output signal corresponding to the first output signal outputted from the first-stage amplifier circuit through the connection node. The first switch has one end and another end. The one end is coupled to the connection node. The first switch allows impedance and a voltage at the connection node to change.

A programmable resistance circuit provides a selected resistance by configuring a reference resistor to exhibit an effective resistance, in an operational sense, by achieving an average output voltage between a source line and a return line in the programmable resistance circuit. The average output voltage corresponds to the effective resistance. The effective resistance is achieved by utilizing a modulated voltage source to bias a transistor and intermittently draw current across the reference resistor according to the duty cycle of the modulated voltage source. A programmed resistance circuit can produce a selected resistance corresponding to button selection zones of a vehicle user interface when connected to a remote circuit that acts according to a user selection.

Programmable clamping methods and devices providing adjustable clamping powers to accommodate different applications and requirements are disclosed. The described devices can use switchable clamping circuits having different structures, body-controlled clamping circuits, or clamping circuits adjusting their input power levels using programmable resistive ladders. Examples of how the disclosed devices can be combined to improve design flexibility are also provided.

Programmable clamping methods and devices providing adjustable clamping powers to accommodate different applications and requirements are disclosed. The described devices can use switchable clamping circuits having different structures, body-controlled clamping circuits, or clamping circuits adjusting their input power levels using programmable resistive ladders. Examples of how the disclosed devices can be combined to improve design flexibility are also provided.

A comparator circuit outputs first and second digital signals corresponding to differential signals to a flip-flop having a predetermined forbidden input combination. A converter circuit performs differential amplification for the differential signals and converts the resultant signals to first and second signals that are complementary digital signals. A logic circuit performs predetermined logical operation, and when the logical values of the first and second signals are different from each other, outputs the first and second digital signals corresponding to the logical values of the first and second signals, and when the logical values of the first and second signals are the same, outputs the first and second digital signals having a same value other than the predetermined forbidden input combination.

A preprocessing circuit for a comparator has a high voltage selection circuit, a first constant voltage circuit, a second constant voltage circuit, a first transistor, and a second transistor. The high voltage selection circuit receives a first voltage and a second voltage, and provides a selected voltage. The first constant voltage circuit provides a first clamping voltage based on the selected voltage, and the second constant voltage circuit provides a second clamping voltage based on the selected voltage. The first transistor receives the first voltage and the first clamping voltage, and provides a first comparison voltage to a first comparison terminal of the comparator. The second transistor receives the second voltage and the second clamping voltage, and provides a second comparison voltage to a second comparison terminal of the comparator.

A comparator circuit includes a zeroth capacitor having a first terminal fed with an input voltage, a zeroth inverter having an input terminal connected to a second terminal of the zeroth capacitor at a zeroth node, a first capacitor having a first terminal connected to the output terminal of the zeroth inverter at a first node, a first inverter having an input terminal connected to a second terminal of the first capacitor at a second node, a second inverter having an input terminal connected to the output terminal of the first inverter at a third node, a zeroth switch switching conduction between the zeroth and first nodes, a first switch switching conduction between the second and third nodes, a second switch switching conduction between the first and third nodes, and a third switch switching conduction between the third node and the output terminal of the second inverter.

A comparator circuit includes a zeroth capacitor having a first terminal fed with an input voltage, a zeroth inverter having an input terminal connected to a second terminal of the zeroth capacitor at a zeroth node, a first capacitor having a first terminal connected to the output terminal of the zeroth inverter at a first node, a first inverter having an input terminal connected to a second terminal of the first capacitor at a second node, a second inverter having an input terminal connected to the output terminal of the first inverter at a third node, a zeroth switch switching conduction between the zeroth and first nodes, a first switch switching conduction between the second and third nodes, a second switch switching conduction between the first and third nodes, and a third switch switching conduction between the third node and the output terminal of the second inverter.

This application relates to methods and apparatus for voltage control, and in particular to maintain safe voltages for components of audio driving circuits that are operable in a high voltage mode. An audio driving circuit (100) may include a power supply module (106) and may be operable such that, in use, a voltage magnitude at a source terminal of at least a first transistor (306, 309, 603, 605) of the audio driving circuit can exceed its gate-source voltage tolerance. A voltage generator (111 P) is configured to output a first intermediate voltage (V.sub.SAFEP) to an intermediate voltage path for use as a gate control voltage for at least the first transistor, to maintain its gate-source voltage below tolerance. An intermediate path voltage clamp (114P) is provided for selectively clamping the intermediate voltage path to a voltage level, so as to maintain the magnitude of the gate-source voltage of the first transistor below tolerance. The voltage clamp (114P) is enabled by a reset condition (RST) for the audio driving circuit.