This application relates to methods and apparatus for voltage control, and in particular to maintain safe voltages for components of audio driving circuits that are operable in a high voltage mode. An audio driving circuit (100) may include a power supply module (106) and may be operable such that, in use, a voltage magnitude at a source terminal of at least a first transistor (306, 309, 603, 605) of the audio driving circuit can exceed its gate-source voltage tolerance. A voltage generator (111 P) is configured to output a first intermediate voltage (V.sub.SAFEP) to an intermediate voltage path for use as a gate control voltage for at least the first transistor, to maintain its gate-source voltage below tolerance. An intermediate path voltage clamp (114P) is provided for selectively clamping the intermediate voltage path to a voltage level, so as to maintain the magnitude of the gate-source voltage of the first transistor below tolerance. The voltage clamp (114P) is enabled by a reset condition (RST) for the audio driving circuit.

A voltage monitoring circuit monitors a magnitude relationship between a monitoring target voltage and a determination voltage and is capable of suppressing the influence of an offset of a reference voltage upon the determination voltage and setting the determination voltage as desired. The voltage monitoring circuit includes: an input terminal, applied with a monitoring target voltage or a divided voltage of the monitoring target voltage; a reference voltage generating circuit, generating a first reference voltage; a linear power circuit, converting the first reference voltage to a second reference voltage; a feedback resistor, generating a divided voltage of the second reference voltage, and negatively feeding back the divided voltage of the second reference voltage to the linear power circuit; and a comparing portion, comparing the second reference voltage with the monitoring target voltage or the divided voltage of the monitoring target voltage applied to the input terminal.

A circuit and method are provided to monitor a clock for a data processor. The method includes receiving a clock signal and producing a first voltage proportional to a frequency of the clock signal. The first voltage is converted to a digital signal. During an initialization mode, the method ensures the clock signal is at a desired frequency and scales the digital signal using a first configurable ratio to produce a high threshold value. When changing from the initialization mode to an operating mode, the method ceases to scale the digital signal and maintains the high threshold value. During the operating mode, the method compares the digital signal to the high threshold value to determine if the clock signal has been increased in frequency beyond a desired level, and if so, triggers an overclock alert to a system management circuit of the data processor.

A circuit and method are provided to monitor a clock for a data processor. The method includes receiving a clock signal and producing a first voltage proportional to a frequency of the clock signal. The first voltage is converted to a digital signal. During an initialization mode, the method ensures the clock signal is at a desired frequency and scales the digital signal using a first configurable ratio to produce a high threshold value. When changing from the initialization mode to an operating mode, the method ceases to scale the digital signal and maintains the high threshold value. During the operating mode, the method compares the digital signal to the high threshold value to determine if the clock signal has been increased in frequency beyond a desired level, and if so, triggers an overclock alert to a system management circuit of the data processor.

A high-speed voltage clamping circuit includes p-type field effect transistor (PFET) biasing circuit, an n-type field effect transistor (NFET) biasing circuit, and a field effect transistor (FET) clamp circuit. The PFET biasing circuit is configured to generate a PFET biasing voltage. The NFET biasing circuit is configured to generate a NFET biasing voltage. The FET clamp circuit is in signal communication with the PFET biasing circuit and the NFET biasing circuit. The PFET biasing circuit controls operation of the clamping circuit in response to a voltage overshoot event and the NFET biasing circuit controls operation of the clamping circuit in response to a voltage undershoot event.

A high-speed voltage clamping circuit includes p-type field effect transistor (PFET) biasing circuit, an n-type field effect transistor (NFET) biasing circuit, and a field effect transistor (FET) clamp circuit. The PFET biasing circuit is configured to generate a PFET biasing voltage. The NFET biasing circuit is configured to generate a NFET biasing voltage. The FET clamp circuit is in signal communication with the PFET biasing circuit and the NFET biasing circuit. The PFET biasing circuit controls operation of the clamping circuit in response to a voltage overshoot event and the NFET biasing circuit controls operation of the clamping circuit in response to a voltage undershoot event.

The present disclosure provides a comparator and a decision feedback equalization circuit. The comparator includes: a first sampling circuit configured to generate, under the control of a first control signal and a clock signal, first differential signals according to a signal to be compared and a first reference signal; a first positive feedback circuit configured to accelerate a difference between the first differential signals; a second sampling circuit configured to generate, under the control of a second control signal and the clock signal, second differential signals according to the signal to be compared and a second reference signal, where the first reference signal is larger than the second reference signal; a second positive feedback circuit configured to accelerate a difference between the second differential signals.

A voltage converter comprising: a bootstrap circuit, comprising an output capacitor, an error amplifier, a charging control circuit and a charging circuit. The charging control circuit comprises: a detection circuit, configured to detect an output voltage of the output capacitor to generate a detection signal; and a power limiting circuit, configured to clamp an output voltage of the error amplifier to a specific range based on the detection signal. The charging circuit is configured to generate a charging signal according the output voltage of the error amplifier to the bootstrap circuit, to charge the output capacitor.

A voltage converter comprising: a bootstrap circuit, comprising an output capacitor, an error amplifier, a charging control circuit and a charging circuit. The charging control circuit comprises: a detection circuit, configured to detect an output voltage of the output capacitor to generate a detection signal; and a power limiting circuit, configured to clamp an output voltage of the error amplifier to a specific range based on the detection signal. The charging circuit is configured to generate a charging signal according the output voltage of the error amplifier to the bootstrap circuit, to charge the output capacitor.

A high-speed voltage clamping circuit includes p-type field effect transistor (PFET) biasing circuit, an n-type field effect transistor (NFET) biasing circuit, and a field effect transistor (FET) clamp circuit. The PFET biasing circuit is configured to generate a PFET biasing voltage. The NFET biasing circuit is configured to generate a NFET biasing voltage. The FET clamp circuit is in signal communication with the PFET biasing circuit and the NFET biasing circuit. The PFET biasing circuit controls operation of the clamping circuit in response to a voltage overshoot event and the NFET biasing circuit controls operation of the clamping circuit in response to a voltage undershoot event.