A high-speed voltage clamping circuit includes p-type field effect transistor (PFET) biasing circuit, an n-type field effect transistor (NFET) biasing circuit, and a field effect transistor (FET) clamp circuit. The PFET biasing circuit is configured to generate a PFET biasing voltage. The NFET biasing circuit is configured to generate a NFET biasing voltage. The FET clamp circuit is in signal communication with the PFET biasing circuit and the NFET biasing circuit. The PFET biasing circuit controls operation of the clamping circuit in response to a voltage overshoot event and the NFET biasing circuit controls operation of the clamping circuit in response to a voltage undershoot event.

To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch. Due to change in the potential of the output terminal of the comparator, the reference potential is changed by capacitive coupling of the second capacitor.

An analog switch circuit includes: a switch unit and a control circuit, wherein the control circuit includes a sensor circuit and a gate-source voltage adjustment circuit. The switch unit operates a first switch therein according to a first gate-source voltage, to convert an input signal of an input terminal to an output signal of an output terminal. The sensor circuit is coupled between the input terminal and the output terminal, and generates a sensing signal according to a voltage difference between the input signal and the output signal. The gate-source voltage adjustment circuit is coupled to the sensor circuit, and adaptively adjusts the first gate-source voltage according to the sensing signal, to maintain the conduction resistance of the switch unit at a constant while the voltage difference changes.

To prevent occurrence of an input voltage dependent error due to an input parasitic capacitance. A comparator includes: a first transistor and a second transistor that include two sources connected to each other, two gates to which a differential input signal pair are input, and two drains that output a differential output signal pair corresponding to a difference signal of the differential input signal pair; a third transistor that is connected between both the sources of the first transistor and the second transistor and a first reference voltage node, the third transistor being switched on or off in accordance with logic of a first signal; and a fourth transistor that is connected between both the sources of the first transistor and the second transistor and a second reference voltage node, the fourth transistor being switched on or off in accordance with logic of a second signal having logic different from the logic of the first signal.

A pulse generation circuit in a quantum controller operates synchronously with a pulse computation circuit. The pulse generation circuit generates a pulse associated with a quantum element operation. The pulse computation circuit is able to determine characteristics of a signal that is based on the pulse. These characteristics are used by the pulse generation circuit to modify the pulse.

An apparatus including a proportional gain circuit, an integral gain circuit, a limit circuit, a gain booster circuit and a combiner. The gain circuits apply a proportional gain and an integral gain to an error signal, and the combiner combines both gained error signals to provide a control signal. The limit circuit applies a limit function that limits the proportional gain to a magnitude. The gain booster circuit increases gain while the limit function is being applied. The increased gain may be applied to only the integral gain, or to both the integral and proportional gains such as by boosting gain of the error signal. The apparatus may be a regulator that may include multiple control loops providing multiple error signals, in which a mode selector selects one of the error signals to control regulation. The limit function increases stability while the boosted gain improves transient response during mode transitions.

An apparatus including a proportional gain circuit, an integral gain circuit, a limit circuit, a gain booster circuit and a combiner. The gain circuits apply a proportional gain and an integral gain to an error signal, and the combiner combines both gained error signals to provide a control signal. The limit circuit applies a limit function that limits the proportional gain to a magnitude. The gain booster circuit increases gain while the limit function is being applied. The increased gain may be applied to only the integral gain, or to both the integral and proportional gains such as by boosting gain of the error signal. The apparatus may be a regulator that may include multiple control loops providing multiple error signals, in which a mode selector selects one of the error signals to control regulation. The limit function increases stability while the boosted gain improves transient response during mode transitions.

A mirror clamp circuit includes a comparator having a first input terminal connectable to a first control terminal of a transistor having the first control terminal connected to the other terminal of a resistor of which one terminal is fed with an output voltage and a first terminal fed with a reference potential and a second input terminal fed with a reference voltage, a transistor switch having a second control terminal fed with a control terminal voltage based on a comparison signal output from the comparator and inserted between the first control terminal and the reference potential, an OR circuit fed with a signal based on the control terminal voltage and the output voltage, and a current feeder configured to change the amount of current fed to the comparator based on the output of the OR circuit.

A power module apparatus includes a power substrate, at least one power device electrically connected to the power substrate and a gate-source board mounted relative to the power substrate, the gate-source board electrically connected to the at least one power device, a housing secured to the power substrate, and a clamping circuit electrically connected to the at least one power device. The clamping circuit being configured to reduce a voltage charge up at a gate of the at least one power device to within 8 V of a desired voltage.

A power module apparatus includes a power substrate, at least one power device electrically connected to the power substrate and a gate-source board mounted relative to the power substrate, the gate-source board electrically connected to the at least one power device, a housing secured to the power substrate, and a clamping circuit electrically connected to the at least one power device. The clamping circuit being configured to reduce a voltage charge up at a gate of the at least one power device to within 8 V of a desired voltage.