A method is described for controlling switching edges for switched output stages, in which a voltage at a switching node of the output stage is detected; a reference time is started when the voltage reaches a predefined reference value; the steepness of the switching edge is reduced if the voltage has reached a second predefined reference value at an end of the reference time; and the steepness of the switching edge is increased if the voltage has not reached the second predefined reference value at the end of the reference time. Furthermore, a control device for adjusting switching edges for switched output stages is provided.

A communication apparatus is one of a plurality of communication apparatuses included in a communication system where a first communication apparatus transmits data via a transmission path in synchronization with communication by a second communication apparatus. The communication apparatus includes a switching element setting a signal level on the transmission path to a dominant level by being turned on; a driving circuit driving the switching element. and a control circuit giving an on command that instructs the driving circuit to turn the switching element on in response to an edge at which a signal level on the transmission path changes from a recessive level to a dominant level being detected. The driving circuit or the control circuit is further configured to shorten a delay time from when the edge is detected to when the switching element is turned on.

A communication apparatus is one of a plurality of communication apparatuses included in a communication system where a first communication apparatus transmits data via a transmission path in synchronization with communication by a second communication apparatus. The communication apparatus includes a switching element setting a signal level on the transmission path to a dominant level by being turned on; a driving circuit driving the switching element. and a control circuit giving an on command that instructs the driving circuit to turn the switching element on in response to an edge at which a signal level on the transmission path changes from a recessive level to a dominant level being detected. The driving circuit or the control circuit is further configured to shorten a delay time from when the edge is detected to when the switching element is turned on.

An input stage configured to differentially amplify an input signal and an output signal, a first current mirror and a second current mirror configured to receive a differential current from the input stage, an output stage including first and second output transistors, respectively including a gate connected to the first and second current mirrors, and a slew rate compensation circuit configured to (i) mirror a comparison current generated by comparing a voltage of a first input signal with a voltage of a second input signal, and (ii) provide the mirrored comparison current to the gate of the first or second output transistor.

Some embodiments include a nonlinear transmission line system comprising: a power supply providing voltages greater than 100 V; a high frequency switch electrically coupled with the power supply; a nonlinear transmission line electrically coupled with the switch; an antenna electrically coupled with the nonlinear transmission line; and an energy recovery circuit comprising a diode and an inductor electrically coupled with the power supply and the antenna.

Some embodiments include a nonlinear transmission line system comprising: a power supply providing voltages greater than 100 V; a high frequency switch electrically coupled with the power supply; a nonlinear transmission line electrically coupled with the switch; an antenna electrically coupled with the nonlinear transmission line; and an energy recovery circuit comprising a diode and an inductor electrically coupled with the power supply and the antenna.

A circuit includes first to third transistors. The first transistor includes a first terminal coupled to a first voltage, and a second terminal coupled to a connection. The second transistor includes a gate terminal coupled to the gate terminal of the first transistor, a first terminal coupled to a second voltage, and a second terminal coupled to the connection. The third transistor includes a first terminal coupled to the connection, a second terminal coupled to a node between the second terminals of the first and second transistors. The third transistor is controlled to be turned ON at a beginning of a first edge of a driving signal on the connection to pull a voltage of the driving signal on the first edge toward a threshold voltage, and be turned OFF in response to and after the voltage of the driving signal on the first edge reaching the threshold voltage.

A circuit includes first to third transistors. The first transistor includes a first terminal coupled to a first voltage, and a second terminal coupled to a connection. The second transistor includes a gate terminal coupled to the gate terminal of the first transistor, a first terminal coupled to a second voltage, and a second terminal coupled to the connection. The third transistor includes a first terminal coupled to the connection, a second terminal coupled to a node between the second terminals of the first and second transistors. The third transistor is controlled to be turned ON at a beginning of a first edge of a driving signal on the connection to pull a voltage of the driving signal on the first edge toward a threshold voltage, and be turned OFF in response to and after the voltage of the driving signal on the first edge reaching the threshold voltage.

Methods and systems are described for generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal based on a comparison of one or more phases of the local oscillator signal to one or more phases of a received reference clock, generating a plurality of phase-specific quadrature error signals, each phase-specific quadrature error signal associated with a respective phase of the plurality of phases of the local oscillator signal, each phase-specific quadrature error signal based on a comparison of the respective phase to two or more other phases of the local oscillator signal, and adjusting each delay stage according to a corresponding phase-specific quadrature error signal of the plurality of phase-specific quadrature error signals and the loop error signal.

A slew rate boosting circuit, a source driver chip and a display device are provided in the present disclosure. The slew rate boosting circuit comprises: a first latch configured to receive and store first data; a second latch configured to receive and store second data, the second data being next to the first data; a first level shifter; an amplifier; and a slew rate boosting module configured to receive a high voltage data signal as current input data, and adjust a slew rate of an output stage of the amplifier according to a value of a specified bit of the first data, a value of a specified bit of the second data and the current input data.