A system and method are described for calibrating a clock used in data transmission. In one example, dynamic phase adjustment circuitry can be used for any of a variety of different protocols to shift the clock phase with respect to a data signal. In the most typical example, the clock phase is shifted 90 degrees relative to a transmission data signal. The dynamic phase adjustment circuitry can use two cascaded programmable delay lines coupled in series. Each programmable delay line represents a half phase delay of 90 degrees. A controller can monitor an output of the programmable delay lines and incrementally add or subtract programmable delay line elements until a 180 degree phase is detected relative to a data transmission. An output clock can then be used by applying the result of the calibration delay element to the clock under discussion.

Apparatuses and methods of DLL measurement initialization are disclosed. An example apparatus includes: a clock enable circuit that provides a first clock signal having a half frequency of an input clock signal and second clock signals having a quarter frequency of the input clock signal; a coarse delay that provides the first clock signal with a coarse delay; a fine delay that provides the first clock signal with the coarse delay and a fine delay as an output clock signal; a model delay having a feedback delay equivalent to a sum of delays of an input stage and an output stage, and provides a feedback signal that is the output clock signal with the feedback delay; and a measurement initialization circuit that performs measurement initialization. The measurement initialization circuit includes synchronizers that receive the feedback signal and the second clock signals, and provide a stop signal to the coarse delay.

Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.

Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.

A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

A signal may be arbitrarily delayed in discrete steps by an arbitrary delay buffer having an analog delay and a digital delay. An analog delay may have a number of selectable delay stages (e.g. ring oscillator with VCDL stages). A digital delay may have rising and falling edge detectors, resettable ring oscillators that oscillate in response to rising or falling edges and counters to count oscillations and generate rising and falling edge delay signals when oscillation counts reach rising and falling edge delay counts. A resettable ring oscillator may have a resettable stage (e.g. VCDL) that may be enabled and disabled. Selection of one or both digital and analog delays and respective delay times may be based on one or more characteristics. For example, an analog delay may delay an input signal or a delayed input signal received from the digital delay based on input signal frequency or total delay.

A method of frequency doubling includes receiving a first clock that has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase; outputting a second clock using a multiplexer by selecting one of the first phase and the second phase of the first clock in accordance with a third clock; delaying the second clock into a fourth clock using a recirculating delay circuit; and using a divide-by-two circuit to output the third clock in accordance with the fourth clock.

Pulse generation circuitry includes edge generation circuitry and edge combination circuitry. The edge generation circuitry includes a first digital-to-time converter (DTC) configured to input a first phase signal that includes a first phase edge and a second phase signal that includes a second phase edge. The edge generation circuitry is configured to generate a first pulse edge signal comprising a first pulse edge at a selected location between the first phase edge and the second phase edge. The edge combination circuitry is configured to combine the first pulse edge signal and a second pulse edge signal including a second pulse edge to generate a pulse signal.

An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. Such a device can have application in digital clock synchronization circuits, and can also be used for a digital phase modulator that encodes a digital signal. A digital phase rotator has been implemented in superconducting integrated circuit technology, using rapid single-flux-quantum logic (RSFQ). This circuit can exhibit positive or negative phase shifts of a multi-phase clock. Arbitrary precision can be obtained by cascading a plurality of phase rotator stages. Such a circuit forms a phase-modulator that is the core of a direct digital synthesizer that can operate at multi-gigahertz radio frequencies.