Some embodiments include apparatuses and methods using a clock generator to generate clock signals, the clock signals being out of phase with each other; a transmitting circuit to provide patterns of data at an output of the transmitting circuit responsive to timing of the clock signals; and calculation and control circuitry to calculate an integral nonlinearity vector that represents offsets of transitions of the patterns from respective target positions, and to generate control information based on the integral nonlinearity vector to adjust phases of the clock signals based on the control information.

A wave-generation circuit is provided. A core circuit establishes digital data. A fetch and calculation circuit generates a first data string and a second data string according to the digital data, outputs the first data string via a first pin, and outputs the second data string via a second pin. A latch circuit latches the first and second data strings. The latch circuit uses the first data string as first input data, and use the second data string as second input data. A digital-to-analog conversion circuit receives and converts the first input data and the second input data to generate a first output wave and a second output wave. After the core circuit establishes the digital data, the fetch and calculation circuit, the latch circuit, and the digital-to-analog conversion circuit operate independently of the core circuit to generate the first output wave and the second output wave.

A wave-generation circuit is provided. A core circuit establishes digital data. A fetch and calculation circuit generates a first data string and a second data string according to the digital data, outputs the first data string via a first pin, and outputs the second data string via a second pin. A latch circuit latches the first and second data strings. The latch circuit uses the first data string as first input data, and use the second data string as second input data. A digital-to-analog conversion circuit receives and converts the first input data and the second input data to generate a first output wave and a second output wave. After the core circuit establishes the digital data, the fetch and calculation circuit, the latch circuit, and the digital-to-analog conversion circuit operate independently of the core circuit to generate the first output wave and the second output wave.

A clock generator includes a pulse generator and a duty cycle correction circuit. The pulse generator is configured to receive an input clock signal and generate a pulse signal according to the input clock signal. The duty cycle correction circuit, coupled to the pulse generator, is configured to adjust a duty cycle of the pulse signal to generate an output clock signal.

A clock generator includes a pulse generator and a duty cycle correction circuit. The pulse generator is configured to receive an input clock signal and generate a pulse signal according to the input clock signal. The duty cycle correction circuit, coupled to the pulse generator, is configured to adjust a duty cycle of the pulse signal to generate an output clock signal.

A column analog-to-digital converter and the local counting method is provided. The column analog-to-digital converter includes a plurality of analog-to-digital converters in parallel. Each of the analog-to-digital converters includes a comparator and a counting circuit. The comparator compares the ramp voltage with one of the plurality of column signals to generate a comparator output signal. The counting circuit generates a local clock by means of a voltage-controlled oscillator of the counting circuit according to the base clock and the comparator output signal, counts the base clock and the local clock respectively to generate a first counting output and a second counting output, and combines the first counting output with the second counting output to generate the counting output.

A column analog-to-digital converter and the local counting method is provided. The column analog-to-digital converter includes a plurality of analog-to-digital converters in parallel. Each of the analog-to-digital converters includes a comparator and a counting circuit. The comparator compares the ramp voltage with one of the plurality of column signals to generate a comparator output signal. The counting circuit generates a local clock by means of a voltage-controlled oscillator of the counting circuit according to the base clock and the comparator output signal, counts the base clock and the local clock respectively to generate a first counting output and a second counting output, and combines the first counting output with the second counting output to generate the counting output.

A semiconductor apparatus includes an internal dock generating circuit, a stop controlling circuit, and a data dock generating circuit. The internal clock generating circuit generates, based on a reference clock signal, a plurality of internal clock signals. The stop controlling circuit generates a stop signal and a dock level signal based on the reference clock signal and the plurality of internal clock signals. The data clock generating circuit generates a data clock signal and a complementary data clock signal based on the plurality of internal clock signals, the stop signal, and the clock level signal.

A semiconductor apparatus includes an internal dock generating circuit, a stop controlling circuit, and a data dock generating circuit. The internal clock generating circuit generates, based on a reference clock signal, a plurality of internal clock signals. The stop controlling circuit generates a stop signal and a dock level signal based on the reference clock signal and the plurality of internal clock signals. The data clock generating circuit generates a data clock signal and a complementary data clock signal based on the plurality of internal clock signals, the stop signal, and the clock level signal.

A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.