Injection locked oscillation circuits are applied along clock distribution circuit paths to increase clock signal bandwidth, reduce duty cycle error, reduce quadrature phase error, reduce clock signal jitter, and reduce clock signal power consumption.

The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over ()}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over ()}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over ()}n phase signal in a first mode. The controller is further configured to provide the mode input of each of 2{circumflex over ()}(n1) odd stages with a first steady state signal and the mode input of each of 2{circumflex over ()}(n1) even stages with a second steady state signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with the same periodic binary signal as in the first mode to cause either the 2{circumflex over ()}(n1) odd stages or the 2{circumflex over ()}(n1) even stages to collectively generate a 2{circumflex over ()}(n1) phase signal in a second mode.

A skew compensation circuit includes a common mode generator, a common mode comparator, a common mode detector, and a skew adjustment circuit. The common mode generator generates a common mode voltage according to a first input voltage and a second input voltage. The common mode comparator generates a first comparison voltage and a second comparison voltage according to the common mode voltage. The common mode detector generates a first control voltage, a second control voltage, a third control voltage, and a fourth control voltage according to the first comparison voltage, the second comparison voltage, a first data voltage, and a second data voltage. The skew adjustment circuit generates a first output voltage and a second output voltage according to the first data voltage, the second data voltage, the first control voltage, the second control voltage, the third control voltage, and the fourth control voltage.

A skew compensation circuit includes a common mode generator, a common mode comparator, a common mode detector, and a skew adjustment circuit. The common mode generator generates a common mode voltage according to a first input voltage and a second input voltage. The common mode comparator generates a first comparison voltage and a second comparison voltage according to the common mode voltage. The common mode detector generates a first control voltage, a second control voltage, a third control voltage, and a fourth control voltage according to the first comparison voltage, the second comparison voltage, a first data voltage, and a second data voltage. The skew adjustment circuit generates a first output voltage and a second output voltage according to the first data voltage, the second data voltage, the first control voltage, the second control voltage, the third control voltage, and the fourth control voltage.

An electronic device includes: an acquisition circuit, configured to collect the current environmental information for characterizing the environment of the electronic device; a processing circuit, configured to receive the current environmental information from the acquisition circuit; determine a target frequency control word corresponding to the current environmental information according to a preset expected operating status of the electronic device; and input the target frequency control word to the TAF-DPS clock generator; the TAF-DPS clock generator, configured to generate a clock signal according to the target frequency control word, and output the clock signal to a functional circuit; the functional circuit, configured to operate in accordance with the clock signal to make the electronic device reach the expected operating status.

An electronic device includes clock generation circuitry. The clock generation circuitry includes a first flip flop receiving as input a device clock and being triggered by an input clock and a second flip flop receiving, as input, output from the first flip flop and being triggered by the input clock. A first inverter receives output from the first flip flop as input and a second inverter receives output from the second flip flop as input. A first AND gate receives, as input, output from the second flip flop and the first inverter, and generates a first clock as output. A second AND gate receives, as input, output from the first flip flop and the second inverter, and generates a second clock as output.

In a signal transmission device having a pulse generator, a RS F/F circuit and a detector, the generator generates a set pulse signal and/or a reset pulse signal when a state of a PWM signal is changed. After the generation of the set pulse signal, the generator continuously generates following pulse signals after elapse of a predetermined period of time counted from the generation of the set pulse signal. The generator adjusts, based on a selector signal, the predetermined period of time counted to a time when the following pulse signal is transmitted at a first time. The detector detects the state of the selector signal based on the predetermined period of time counted from a time when the RS F/F circuit receives the set pulse signal or the reset pulse signal to a time when receiving the following pulse signal at a first time.

A phase rotator receives control signals and thermometer coded signals that specifies the phase of an output signal. The phase rotator may be used, for example, by a clock and data recovery (CDR) circuit to continually rotate the phase of a clock to compensate for phase/frequency mismatches between received data and the clock. The control signals determine the phase quadrant (i.e., 0-90, 90-180, etc.) of the output signal. The thermometer coded signals determine the phase of the output signal within a quadrant by steering a set of bias currents between two or more nodes. The set of bias currents are selected to reduce the non-linearity between the thermometer coded value and the phase of the output signal.

Clock adjustment circuits and clock adjustment methods are provided. The clock adjustment circuit is configured to adjust an input clock to generate an output clock and includes a low-pass filter, a direct current (DC) control circuit, a DC offset amplifier, an amplifier, and an integrator. The low-pass filter filters the input clock to generate a filtered signal. The DC control circuit adjusts a DC voltage based on a control signal. The DC offset amplifier generates an intermediate clock based on the filtered signal and the DC voltage. The amplifier generates the output clock based on the intermediate clock. The integrator generates the control signal based on the output clock. The control signal varies with an average based on the duty cycle of the output clock.

Clock adjustment circuits and clock adjustment methods are provided. The clock adjustment circuit is configured to adjust an input clock to generate an output clock and includes a low-pass filter, a direct current (DC) control circuit, a DC offset amplifier, an amplifier, and an integrator. The low-pass filter filters the input clock to generate a filtered signal. The DC control circuit adjusts a DC voltage based on a control signal. The DC offset amplifier generates an intermediate clock based on the filtered signal and the DC voltage. The amplifier generates the output clock based on the intermediate clock. The integrator generates the control signal based on the output clock. The control signal varies with an average based on the duty cycle of the output clock.