A primary side wireless power transmitter inductively couplable to a secondary side wireless power receiver for supplying power to the wireless power receiver for receiving communications from the secondary side wireless power receiver through the inductive coupling comprises a primary side tank circuit receiving a signal on from the secondary side wireless power receiver. A phase delay or time delay circuit generates a fixed delay clock signal. A sample and hold circuit samples a tank circuit voltage utilizing the fixed phase or time delayed clock signal. A comparator is coupled to an output of the sample and hold circuit for extracting data or commands from the signal stream. A method of operating a primary side wireless transmitter inductively coupled to a secondary side wireless power receiver for supplying power to the wireless power receiver to power a load coupled to the receiver is also disclosed.

A primary side wireless power transmitter inductively couplable to a secondary side wireless power receiver for supplying power to the wireless power receiver for receiving communications from the secondary side wireless power receiver through the inductive coupling comprises a primary side tank circuit receiving a signal on from the secondary side wireless power receiver. A phase delay or time delay circuit generates a fixed delay clock signal. A sample and hold circuit samples a tank circuit voltage utilizing the fixed phase or time delayed clock signal. A comparator is coupled to an output of the sample and hold circuit for extracting data or commands from the signal stream. A method of operating a primary side wireless transmitter inductively coupled to a secondary side wireless power receiver for supplying power to the wireless power receiver to power a load coupled to the receiver is also disclosed.

Techniques are described for peak-adaptive sampling demodulation for radiofrequency transceivers. For example, a tag input signal is received via an antenna, from which a clock input signal can be extracted. Multiple clock output signals can be generated responsive to the extracted clock input signal, such that each has a different respective phase. A multiphase selector can identify the one of the clock output signals that has the respective phase that is closest to the phase of the tag input signal and is best suited for sampling the peak of the tag input signal, accordingly. A single-path detector can generate a data output signal by using the identified clock output signal to sample the tag input signal, and the detector can filter and amplify the data output signal using small-signal devices.

Techniques are described for peak-adaptive sampling demodulation for radiofrequency transceivers. For example, a tag input signal is received via an antenna, from which a clock input signal can be extracted. Multiple clock output signals can be generated responsive to the extracted clock input signal, such that each has a different respective phase. A multiphase selector can identify the one of the clock output signals that has the respective phase that is closest to the phase of the tag input signal and is best suited for sampling the peak of the tag input signal, accordingly. A single-path detector can generate a data output signal by using the identified clock output signal to sample the tag input signal, and the detector can filter and amplify the data output signal using small-signal devices.

Techniques are described for peak-adaptive sampling demodulation for radiofrequency transceivers. For example, a tag input signal is received via an antenna, from which a clock input signal can be extracted. Multiple clock output signals can be generated responsive to the extracted clock input signal, such that each has a different respective phase. A multiphase selector can identify the one of the clock output signals that has the respective phase that is closest to the phase of the tag input signal and is best suited for sampling the peak of the tag input signal, accordingly. A single-path detector can generate a data output signal by using the identified clock output signal to sample the tag input signal, and the detector can filter and amplify the data output signal using small-signal devices.

A control system for controlling a mechanically commutated direct current electric motor and corresponding method of operation are provided. The control system includes a motor current sensing circuit for sensing a motor current comprising a plurality of ripples due to commutation of the motor and outputting a motor current signal. The control system also includes a controller including a finite state machine unit and is configured to detect the plurality of ripples in the motor current and to determine whether each of the plurality of ripples is a valid ripple using the finite state machine unit. The controller is also configured to count the plurality of ripples determined to be valid using the finite state machine unit and to determine at least one of a motor rotational position and a motor speed of the motor based on a quantity of the plurality of ripples determined to be valid.

A control system for controlling a mechanically commutated direct current electric motor and corresponding method of operation are provided. The control system includes a motor current sensing circuit for sensing a motor current comprising a plurality of ripples due to commutation of the motor and outputting a motor current signal. The control system also includes a controller including a finite state machine unit and is configured to detect the plurality of ripples in the motor current and to determine whether each of the plurality of ripples is a valid ripple using the finite state machine unit. The controller is also configured to count the plurality of ripples determined to be valid using the finite state machine unit and to determine at least one of a motor rotational position and a motor speed of the motor based on a quantity of the plurality of ripples determined to be valid.

An apparatus includes a voltage divider circuit including a plurality of series-connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage. The apparatus further includes a switch driver coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak amplitude.

An apparatus includes a voltage divider circuit including a plurality of series-connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage. The apparatus further includes a switch driver coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak amplitude.

A power converter which converts electrical power at an input voltage into electrical power at an output voltage is presented. It has a power stage with a high side switching element, a low side switching element and an inductor. The power converter has a voltage-to-current converter coupled to the power stage to convert a voltage indicative of a current flowing into the inductor into an indicator current. A peak current detector receives the indicator current to determine a pedestal component of the indicator current in a first time interval during which the high side switching element is open, and to generate a calibrated indicator current by subtracting the pedestal component from the indicator current. The peak current detector compares the calibrated indicator current with a threshold value for detecting a more precise peak current flowing into the inductor, taking into account the effects of temperature or circuit aging.