A peak detector comprises multiple small-size amplitude detection circuits coupled in parallel to signal inputs at which a signal is received from a VCO. Each amplitude detection circuit generates a voltage on an output, indicating a voltage peak or amplitude of a first signal input and a second signal input (specifically, differential output of VCO). At a given time, only one small-size amplitude detection circuit is activated to load VCO, reducing the impact on LC resonant frequency. The plurality of small-size detection circuits work sequentially, and an automatic averaging of their outputs can significantly improve the peak detector fluctuation (caused by process variation and device mismatch) compared to each single small-size amplitude detection circuit.

A power supply device includes a power switch that is switched according to a gate voltage. A sense resistor receives a switch current that flows through the power switch to develop a sense voltage. A peak of a primary-side current is detected from the sense voltage. The gate driver has a pair of switches for generating the gate voltage in accordance with a control signal. When a low-side switch of the gate driver is turned on according to the control signal, the gate voltage of the power switch decreases as a sink current flows from the gate of the power switch via the transistor.

A power supply device includes a power switch that is switched according to a gate voltage. A sense resistor receives a switch current that flows through the power switch to develop a sense voltage. A peak of a primary-side current is detected from the sense voltage. The gate driver has a pair of switches for generating the gate voltage in accordance with a control signal. When a low-side switch of the gate driver is turned on according to the control signal, the gate voltage of the power switch decreases as a sink current flows from the gate of the power switch via the transistor.

The present disclosure describes aspects of a fast settling peak detector. In some aspects, a peak detector circuit includes a first transistor having a gate coupled to an input of the circuit at which a signal is received and a drain coupled to a source of a second transistor. Current may flow in the first and second transistors responsive to the signal. The circuit also includes a third transistor having a gate coupled, via a signal-inverting component, to the input of the circuit and a drain coupled to a source of a fourth transistor. Through an inversion of the signal, other current flowing in the third and fourth transistor can reduce or cancel a frequency component of the current in the first and second transistors. In some cases, this precludes a need to filter the frequency component from an output of the circuit.

The present disclosure describes aspects of a fast settling peak detector. In some aspects, a peak detector circuit includes a first transistor having a gate coupled to an input of the circuit at which a signal is received and a drain coupled to a source of a second transistor. Current may flow in the first and second transistors responsive to the signal. The circuit also includes a third transistor having a gate coupled, via a signal-inverting component, to the input of the circuit and a drain coupled to a source of a fourth transistor. Through an inversion of the signal, other current flowing in the third and fourth transistor can reduce or cancel a frequency component of the current in the first and second transistors. In some cases, this precludes a need to filter the frequency component from an output of the circuit.

A peak/bottom detection circuit is disclosed. A comparator compares a voltage of one of three or more capacitors with an input voltage. A calculation amplifier amplifies the voltage of one of the three or more capacitors. Each of three or more switches respectively corresponding to the three or more capacitors connects a corresponding capacitor among the three or more capacitors to one of the comparator, the calculation amplifier, and a source of the input voltage. A controller generates control signals for sequentially switching connection destinations of the three or more capacitors and to supply the control signals to the three or more switches, respectively, in which the connection destinations of three capacitors among the three or more capacitors are different from each other.

In certain embodiments, a system for detecting a peak laser pulse includes a laser, a photodiode configured to detect pulses emitted by the laser, and circuitry for detecting a peak pulse timing of the laser. The circuitry is configured to receive a periodic series of voltage signals based on laser pulses detected by the photodiode, stretch the voltage signals, and obtain sampled voltages from the stretched voltage signals using periodic control signals. The circuitry is further configured to shift the timing of the periodic control signals, compare the sampled voltages for respective timings of the control signals, and select an optimal control signal timing based on the comparison.

In certain embodiments, a system for detecting a peak laser pulse includes a laser, a photodiode configured to detect pulses emitted by the laser, and circuitry for detecting a peak pulse timing of the laser. The circuitry is configured to receive a periodic series of voltage signals based on laser pulses detected by the photodiode, stretch the voltage signals, and obtain sampled voltages from the stretched voltage signals using periodic control signals. The circuitry is further configured to shift the timing of the periodic control signals, compare the sampled voltages for respective timings of the control signals, and select an optimal control signal timing based on the comparison.

A peak detector circuit includes a first capacitor coupled to an inverter and a first switch in parallel with the inverter. An input of the inverter couples to second and third switches. The second switch couples to an input voltage node. The third switch couples to an output voltage node of the peak detector circuit. The peak detector circuit includes a second capacitor coupled to the third switch and a third capacitor coupled to the second capacitor by way of a fourth switch. The third capacitor couples via a fifth switch to a power supply voltage node or a ground. A periodic control signal causes the first, second, and third switches to repeatedly open and close and a second control signal causes the fourth and fifth switches to open and close to adjust an output voltage on the output voltage node towards an input voltage on the input voltage node.

A peak detector circuit includes a first capacitor coupled to an inverter and a first switch in parallel with the inverter. An input of the inverter couples to second and third switches. The second switch couples to an input voltage node. The third switch couples to an output voltage node of the peak detector circuit. The peak detector circuit includes a second capacitor coupled to the third switch and a third capacitor coupled to the second capacitor by way of a fourth switch. The third capacitor couples via a fifth switch to a power supply voltage node or a ground. A periodic control signal causes the first, second, and third switches to repeatedly open and close and a second control signal causes the fourth and fifth switches to open and close to adjust an output voltage on the output voltage node towards an input voltage on the input voltage node.